用QuartusII实现半加器全加器2-4译码器BCD码加法器计数器交通灯

Posted 2020-08-31 Cassie_hkx

6、交通灯实现代码
module light(clk,set,chan,light,out);
input clk,set,chan;
output reg[1:0] light;
output reg[3:0] out;
[email protected](posedge clk or posedge chan or posedge set)
	if(set==1)
	begin
		out=0;
		light=01;
	end
	else 	if(chan==1)
			begin
				if(light<2)
					light=2;
				else
					light=01;
			end	
	else 
	begin
		if(out>=5)
		begin
				out=0;
				if(light<2)
					light=light+1;
				else
					light=light-1;	
		end
		else
			out=out+1;
	end
endmodule			

 

1、半加器实现代码 module HalfAdder (A, B, Sum, Carry) ; //定义模块名HalfAdder input A, B; //声明端口A, B为输入 output Sum, Carry; //声明端口Sum, Carry为输出 assign Sum = A ^ B; //将A^B的和赋值给Sum assign Carry = A & B; //将A&B的进位赋值给Carry endmodule //模块结束关键字

2、全加器实现代码
module HalfAdd(X , Y, SUM, C_out);//半加器模块
input X, Y;
output SUM, C_out;
	xor u_xor (SUM, X, Y); // 门级展语实例
	and u_and (C_out , X, Y); // 门级原语实例
endmodule
module HKX(X , Y, C_in , SUM, C_out) ;//全加器模块
input X, C_in,Y;
output SUM, C_out;
wire HalfAdd_A_SUM;
wire HalfAdd_A_COUT;
wire HalfAdd_B_COUT;
or u_or (C_out, HalfAdd_A_COUT, HalfAdd_B_COUT); 
//门级原语实例
HalfAdd u_HalfAdd_A (.X(X),.Y (Y),
	.SUM (HalfAdd_A_SUM),
	.C_out (HalfAdd_A_COUT) ); //半加器实例A
HalfAdd u_HalfAdd_B (.X (C_in),.Y(HalfAdd_A_SUM),
	.SUM (SUM),.C_out (HalfAdd_B_COUT) ); 
						//半加器实例B
Endmodule

 

3、2-4译码器实现代码
    `timescale 1ns/100ps
    module Decoder_2x4 (A, B, EN, Z) ;
    input A, B, EN;
    output [ 0 :3] Z;
    wire Abar, Bbar;
  	    assign #1 Abar = ~ A; // 语句1。
   	    assign #1 Bbar = ~ B; // 语句2。
       assign #2 Z[0] = ~ (Abar & Bbar & EN ) ;// 语句3。
       assign #2 Z[1] = ~ (Abar & B & EN) ;// 语句4。
       assign #2 Z[2] = ~ (A & Bbar & EN) ;// 语句5。
       assign #2 Z[3] = ~ ( A & B & EN) ;// 语句6。
endmodule

 

4、BCD码加法器实现代码
module BCD(ina,inb,cout,sum);
    input [3:0] ina,inb;
    output cout;
    output [3:0]sum;
    assign {cout,sum}=((ina+inb)>9)?(ina+inb+6):(ina+inb);
endmodule  

 

5、计数器实现代码
module counter_8(en,clock,reset,out,cin);
	input clock,en,reset;
	input [3:0] cin;
	output [3:0] out;
	reg [3:0] out;
	always @(posedge clock or negedge reset)
	if(!reset) 
		out=cin;
	else if(en)
		out=out+1;
endmodule