Upgrade Zynq-7000 XIP reference design to Xilinx SDK 2018.3

Posted 2021-03-03 hankfu

 

付汉杰 [e-mail] 

• 1. Introduction
• 2. Vivado project
• 3. FSBL
• 4. C Application
• 5. C++ Application
• 6. Create boot file
  • 6.1. Example of bootgen.bif
• 7. Tips
  • 7.1. Add ‘xip_mode‘ manually.
  • 7.2. Debugging
  • 7.3. FSBL compilation error
  • 7.4. C++ Application compilation error
• 8. Files

 

1. Introduction

Xilinx provided reference design Zynq-7000 AP SoC Boot - Booting and Running Without External Memory that is helpful to run application in OCM for embedded system without DDR. It was upgraded to Vivado/SDK 2017.3.

Many customers use Xilinx 2018.x/2019.x tools now. So, I upgrade it to 2018.3. Its portability is also improved by reorganizing the source code.

• The new design does not modify the source code in the BSP project.
• All files including customized code are in the application project.
• All modifications are encompassed by one Macro ‘DDRLESS_XIP_SYSTEM‘.

It would be much easy to port it to latest Xilinx tools and other boards.

2. Vivado project

We can use any Vivado project that disables PS DDR controller of Zynq-7000. One AXI timer with name is ‘axi_timer_0‘ should be added in order to run the C application project in the reference design Zynq-7000 AP SoC Boot - Booting and Running Without External Memory.

The reference design, Zynq-7000 AP SoC Boot - Booting and Running Without External Memory, also provided TCL script files ‘project.tcl‘ and ‘system_top.tcl‘ to recreate the hardware project. The string ‘2017.3‘ should be replaced with ‘2018.3‘ in the script file before we recreate the hardware project Because it is created by Vivado 2017.3 and Vivado 2018.3 is used now.

It is easy to create project for Xilinx Dev. Kit by applying board preset setting. Then we enable GP0 AXI master port, add one PL AXI timer to the block design, and connect its interrupt line to ‘IRQ_F2P[0:0]‘. Finally, we leverage Vivado‘s ‘run connection automation‘ to connect the AXI timer to GP0 port. Please check that the AXI timer‘s name is ‘axi_timer_0‘.

MicroZed project

 

We need disable its DDR controller in Vivado project, generate the output products for the block design and export HDF file.

One HDF file is provided for MicroZed 7010 board in the attached files. It can also work with MicroZed 7020 board. Its hardware project can be recreated by executing its TCL script in Vivado console.

3. FSBL

The following files are modified for FSBL of XIP reference design.

fsbl.h
fsbl_handoff.S
fsbl_hooks.c
fsbl_hooks.h
image_mover.c
image_mover.h
lscript.ld
main.c
pcap.c
pcap.h
qspi.c
qspi.h
translation_table.S
xil_exception.c

They are in the directory ‘src‘ of FSBL project. Please note that the FSBL use normal FSBL BSP project now.
Create one new FSBL project and copy aforementioned files from directory "ddrless_xip_packagefsbl_xipsrc" to the directory ‘src‘ of FSBL project. Click ‘Yes‘ when SDK asks whether to overwrite existing files. And add macros ‘FSBL_DEBUG_INFO‘ and ‘DDRLESS_XIP_SYSTEM‘ in the project settings.

Add macro definition

 

4. C Application

The following files are created or modified for C Application of XIP reference design.

Application.c
lscript.ld
startup.s
TimerApp.c
xil_exception.c

They are in the directory ‘src‘ of C Application project. Please note that the C Application use normal C/C++ Application BSP project now.
Create one new empty C Application project, remove file ‘lscript.ld‘, then copy aforementioned files from directory "ddrless_xip_packageApplicationsrc" to the directory ‘src‘ of C Application project. Overwrite existing files if original files are not deleted.

5. C++ Application

The following files are created or modified for C++ Application of XIP reference design.

app.cc
copyRO.cc
cpu_init.S
lscript.ld
startup.s
xil_exception.c

They are in the directory ‘src‘ of C++ Application project. Please note that the C++ Application use normal C/C++ Application BSP project now.
Please create one new empty C++ Application project, remove source code files and linker script files, and copy aforementioned files from directory "ddrless_xip_packageApplication_Cppsrc" to the directory ‘src‘ of C++ Application project.

6. Create boot file

When we create boot file, we must declare that FSBL works in XIP mode, specify each components‘s flash address that must match the flash address used by linker script.
FSBL‘s Flash address starts at 0x2000, Application‘s Flash address starts at 0x700000 in this example. So we declare them in the ‘bootgen.bif‘.

6.1. Example of bootgen.bif

//arch = zynq; split = false; format = BIN
the_ROM_image:
{
	[bootloader, xip_mode, offset = 0x2000]C:prjfsbl_xip_v183.elf
	[offset = 0x200000]C:prjdesign_noddr_wrapper.bit
	[offset = 0x700000]C:prjApplication.elf
}

One example bootgen.bif is provided for both C/C++ applications. Please check it if you encounter problem about booting.

7. Tips

7.1. Add ‘xip_mode‘ manually.

SDK 2018.3 bootimage wizard removes ‘xip_mode‘ after one new file is specified for the boot file. We must add ‘xip_mode‘ to the ‘.bif‘ file manually before we create boot file. Otherwise the boot file fails to boot. There may not be any string printed out by FSBL in the UART console.

7.2. Debugging

We cannot debug the XIP code in single-step mode.

Please debug the application in DDR and make it works well in advance. You can also refer to project "ddrless_xip_packageApplication_normal" that has same functionality of the project ‘Application‘. We can debug it in single-step mode because it runs in DDR.

7.3. FSBL compilation error

We get the following error when we compile FSBL. It can be ignored.

ld.exe: FSBL_XIP.elf: section `.data‘ can‘t be allocated in segment 0

7.4. C++ Application compilation error

We get the following error when we compile C++ Application. It can be ignored.

ld.exe: Application_Cpp.elf: section `.data‘ can‘t be allocated in segment 0

8. Files