Zynq UltraScale+ MPSoC device tree 中 CCF中 clock output数字映射表

Posted 2020-10-10 Kevin_HeYongyuan

目的：方便使用Zynq UltraScale+ MPSoC的朋友们在添加PL侧IP后在对应的devicetree 如何设置对应的clock input参数

预备知识：阅读zynqmp-clk-ccf.dtsi，文档位置  linux-xlnx-xilinx-v2017.1\arch\arm64\boot\dts\xilinx\

原始文件对clock output的定义：

clkc: clkc {
u-boot,dm-pre-reloc;
#clock-cells = <1>;
compatible = "xlnx,zynqmp-clkc";
clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
clock-output-names = "iopll", "rpll", "apll", "dpll",
"vpll", "iopll_to_fpd", "rpll_to_fpd",
"apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
"acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
"dbg_trace", "dbg_tstmp", "dp_video_ref",
"dp_audio_ref", "dp_stc_ref", "gdma_ref",
"dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
"gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
"topsw_main", "topsw_lsbus", "gtgref0_ref",
"lpd_switch", "lpd_lsbus", "usb0_bus_ref",
"usb1_bus_ref", "usb3_dual_ref", "usb0",
"usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
"csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
"gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
"gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
"gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
"uart0_ref", "uart1_ref", "spi0_ref",
"spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
"can0_ref", "can1_ref", "can0", "can1",
"dll_ref", "adma_ref", "timestamp_ref",
"ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt";
};

 

为方便些devicetree，现在列出对应的数字映射关系：

clock-output-names =

0: "iopll", 1:  "rpll", 2:  "apll", 3:  "dpll", 4:  "vpll", 5:  "iopll_to_fpd", 6:  "rpll_to_fpd", 7:  "apll_to_lpd", 8:  "dpll_to_lpd", 9:  "vpll_to_lpd", 10:  "acpu", 11:  "acpu_half", 12:  "dbf_fpd", 13:  "dbf_lpd", 14:  "dbg_trace", 15:  "dbg_tstmp", 16:  "dp_video_ref", 17:  "dp_audio_ref", 18:  "dp_stc_ref", 19:  "gdma_ref", 20:  "dpdma_ref", 21:  "ddr_ref", 22:  "sata_ref", 23:  "pcie_ref", 24:  "gpu_ref", 25:  "gpu_pp0_ref", 26:  "gpu_pp1_ref", 27:  "topsw_main", 28:  "topsw_lsbus", 29:  "gtgref0_ref", 30:  "lpd_switch", 31:  "lpd_lsbus", 32:  "usb0_bus_ref", 33:  "usb1_bus_ref", 34:  "usb3_dual_ref", 35:  "usb0", 36:  "usb1", 37:  "cpu_r5", 38:  "cpu_r5_core", 39:  "csu_spb", 40:  "csu_pll", 41:  "pcap", 42:  "iou_switch", 43:  "gem_tsu_ref", 44:  "gem_tsu", 45:  "gem0_ref", 46:  "gem1_ref", 47:  "gem2_ref", 48:  "gem3_ref", 49:  "gem0_tx", 50:  "gem1_tx", 51:  "gem2_tx", 52:  "gem3_tx", 53:  "qspi_ref", 54:  "sdio0_ref", 55:  "sdio1_ref", 56   "uart0_ref", 57:  "uart1_ref", 58:  "spi0_ref", 59:  "spi1_ref", 60:  "nand_ref", 61:  "i2c0_ref", 62:  "i2c1_ref", 63:  "can0_ref", 64:  "can1_ref", 65:  "can0", 66:  "can1", 67:  "dll_ref", 68:  "adma_ref", 69:  "timestamp_ref", 70:  "ams_ref", 71:  "pl0", 72:  "pl1", 73:  "pl2", 74:  "pl3", 75:  "wdt";

 

PL侧添加AXI接口IP，一般都用的pl0/1/2/3 clock中的一个，比如选择pl0作为clock源，在对应的devicetree中clock input为

 clocks = <&clkc 71>;

 

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