ad_封装_ads828
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module ad_ctrl( clk,rst_n,ad_clk, ad_data,value_x,value_y,q_sig,wren,r_addr,w_addr ); input clk; input rst_n; input [10:0] value_x; input [10:0] value_y; output ad_clk; input [9:0] ad_data; output wren; output [7:0] q_sig; output reg [8:0] r_addr; output reg [8:0] w_addr; assign ad_clk = ~clk; wire [7:0] data_sig; assign data_sig = ad_data[9:2]; ram_ad ram_ad_inst ( .clock ( clk ), .data ( data_sig ), .rdaddress ( r_addr ), .wraddress ( w_addr ), .wren ( wren ), .q ( q_sig ) ); //read ram always @(posedge clk or negedge rst_n) if(!rst_n) r_addr <= ‘d0; else if((value_x >= 0 && value_x < 512) && (value_y >= 0 && value_y <256)) r_addr <= value_x[8:0]; else r_addr <= ‘d0; //write ram reg [1:0] state; always @(posedge clk or negedge rst_n) if(!rst_n)begin w_addr <= ‘d0; state <= ‘d0; end else if((value_x >= 0 && value_x < 512) && (value_y >= 256 && value_y <260))begin case(state) 2‘d0:begin if(data_sig > 128) state <= 1; else state <= ‘d0; end 2‘d1:begin if(w_addr > 510)begin state <= ‘d0; w_addr <= ‘d0; end else begin w_addr <= w_addr + 1‘d1; state <= 2‘d1; end end default:state <= ‘d0; endcase end else w_addr <= ‘d0; //wren reg wren_r; always @(posedge clk or negedge rst_n) if(!rst_n) wren_r <= 1‘d0; else if((value_x >= 0 && value_x < 512) && (value_y >= 0 && value_y <256)) wren_r <= 1‘d0; else if((value_x >= 0 && value_x < 512) && (value_y >= 256 && value_y <260)) wren_r <= 1‘d1; else wren_r <= 1‘d0; assign wren = wren_r; endmodule
set_location_assignment PIN_AF14 -to clk
set_location_assignment PIN_AA14 -to rst_n
set_location_assignment PIN_AF26 -to ad_data[0]
set_location_assignment PIN_AG25 -to ad_data[1]
set_location_assignment PIN_AE24 -to ad_data[2]
set_location_assignment PIN_AF25 -to ad_data[3]
set_location_assignment PIN_AD24 -to ad_data[4]
set_location_assignment PIN_AE23 -to ad_data[5]
set_location_assignment PIN_AB21 -to ad_data[6]
set_location_assignment PIN_AC23 -to ad_data[7]
set_location_assignment PIN_AB17 -to ad_data[8]
set_location_assignment PIN_AA21 -to ad_data[9]
set_location_assignment PIN_AG26 -to ad_clk
set_location_assignment PIN_B13 -to vga_b[0]
set_location_assignment PIN_G13 -to vga_b[1]
set_location_assignment PIN_H13 -to vga_b[2]
set_location_assignment PIN_F14 -to vga_b[3]
set_location_assignment PIN_H14 -to vga_b[4]
set_location_assignment PIN_F15 -to vga_b[5]
set_location_assignment PIN_G15 -to vga_b[6]
set_location_assignment PIN_J14 -to vga_b[7]
set_location_assignment PIN_F10 -to vga_blank
set_location_assignment PIN_A11 -to vga_clk
set_location_assignment PIN_J9 -to vga_g[0]
set_location_assignment PIN_J10 -to vga_g[1]
set_location_assignment PIN_H12 -to vga_g[2]
set_location_assignment PIN_G10 -to vga_g[3]
set_location_assignment PIN_G11 -to vga_g[4]
set_location_assignment PIN_G12 -to vga_g[5]
set_location_assignment PIN_F11 -to vga_g[6]
set_location_assignment PIN_E11 -to vga_g[7]
set_location_assignment PIN_B11 -to vga_hs
set_location_assignment PIN_A13 -to vga_r[0]
set_location_assignment PIN_C13 -to vga_r[1]
set_location_assignment PIN_E13 -to vga_r[2]
set_location_assignment PIN_B12 -to vga_r[3]
set_location_assignment PIN_C12 -to vga_r[4]
set_location_assignment PIN_D12 -to vga_r[5]
set_location_assignment PIN_E12 -to vga_r[6]
set_location_assignment PIN_F13 -to vga_r[7]
set_location_assignment PIN_C10 -to vga_sync
set_location_assignment PIN_D11 -to vga_vs
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