P5 - Verilog流水线CPU
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1 module mips( 2 input clk, 3 input reset 4 ); 5 6 //F级 7 wire [31:0] NewPC; 8 wire [31:0] PC_F; 9 wire Stop; 10 PC PC_P5 ( 11 .Clock(clk), 12 .Reset(reset), 13 .Stop(Stop), 14 .NextPC(NewPC), 15 .PC(PC_F) 16 ); 17 18 wire [31:0] IR_F; 19 IM IM_P5 ( 20 .Address(PC_F[11:2]), 21 .Instr(IR_F) 22 ); 23 24 wire [31:0] IR_D; 25 wire [31:0] PC_D; 26 Reg_D Reg_D_P5 ( 27 .Clock(clk), 28 .Reset(reset), 29 .Enable(Stop), 30 .IR_F(IR_F), 31 .PC_F(PC_F), 32 .IR_D(IR_D), 33 .NPC_D(PC_D) 34 ); 35 //D级 36 37 //D级 38 wire [1:0] RegDst_D; 39 wire RegWrite_D; 40 wire ALUSrc_D; 41 wire MemWrite_D; 42 wire [1:0]MemtoReg_D; 43 wire [1:0] ExtOp_D; 44 wire [3:0] ALUOp_D; 45 wire [2:0] NPCOp_D; 46 ctrl D_ctrl_P5 ( 47 .Op(IR_D[31:26]), 48 .Func(IR_D[5:0]), 49 .RegDst(RegDst_D), 50 .RegWrite(RegWrite_D), 51 .ALUSrc(ALUSrc_D), 52 .MemWrite(MemWrite_D), 53 .MemtoReg(MemtoReg_D), 54 .ExtOp(ExtOp_D), 55 .ALUOp(ALUOp_D), 56 .NPCOp(NPCOp_D) 57 ); 58 59 //forward 60 wire [31:0] WriteData; 61 wire [31:0] PC_E; 62 wire [31:0] AO_M; 63 wire [31:0] PC_M; 64 65 wire [31:0] RD1; 66 wire [2:0] RSDsel; 67 wire [31:0] ReadData1; 68 mux_5_32 MFRSD_P5 ( 69 .a(ReadData1), 70 .b(WriteData), 71 .c(PC_M+8), 72 .d(AO_M), 73 .e(PC_E+8), 74 .select(RSDsel), 75 .y(RD1) 76 ); 77 wire [31:0] RD2; 78 wire [2:0] RTDsel; 79 wire [31:0] ReadData2; 80 mux_5_32 MFRTD_P5 ( 81 .a(ReadData2), 82 .b(WriteData), 83 .c(PC_M+8), 84 .d(AO_M), 85 .e(PC_E+8), 86 .select(RTDsel), 87 .y(RD2) 88 ); 89 //forward 90 91 NPC NPC_P5 ( 92 .Instr(IR_D[25:0]), 93 .PC_F(PC_F), 94 .PC_D(PC_D), 95 .rs(RD1), 96 .A(RD1), 97 .B(RD2), 98 .NPCOp(NPCOp_D), 99 .npc(NewPC) 100 ); 101 102 wire RegWrite_W; 103 wire [4:0] A3_W; 104 wire [31:0] PC_W; 105 GRF GRF_P5 ( 106 .Clock(clk), 107 .Reset(reset), 108 .RegWrite(RegWrite_W), 109 .ReadReg1(IR_D[25:21]), 110 .ReadReg2(IR_D[20:16]), 111 .WriteReg(A3_W), 112 .WriteData(WriteData), 113 .WPC(PC_W), 114 .ReadData1(ReadData1), 115 .ReadData2(ReadData2) 116 ); 117 118 wire [31:0] EXTOut; 119 EXT EXT_P5 ( 120 .Imm_16(IR_D[15:0]), 121 .ExtOp(ExtOp_D), 122 .Imm_32(EXTOut) 123 ); 124 125 wire [31:0] IR_E; 126 wire [31:0] V1_E; 127 wire [31:0] V2_E; 128 wire [31:0] E32_E; 129 wire [4:0] A1_E; 130 wire [4:0] A2_E; 131 wire [4:0] A3_E; 132 Reg_E Reg_E_P5 ( 133 .Clock(clk), 134 .Reset(reset | Stop), 135 .IR_D(IR_D), 136 .RF_RD1(ReadData1), 137 .RF_RD2(ReadData2), 138 .PC4_D(PC_D), 139 .EXT(EXTOut), 140 .Rs_IR_D(IR_D[25:21]), 141 .Rt_IR_D(IR_D[20:16]), 142 .Rd_IR_D(IR_D[15:11]), 143 .IR_E(IR_E), 144 .V1_E(V1_E), 145 .V2_E(V2_E), 146 .A1_E(A1_E), 147 .A2_E(A2_E), 148 .A3_E(A3_E), 149 .E32_E(E32_E), 150 .PC4_E(PC_E) 151 ); 152 //E级 153 154 //E级 155 wire [1:0] RegDst_E; 156 wire RegWrite_E; 157 wire ALUSrc_E; 158 wire MemWrite_E; 159 wire [1:0]MemtoReg_E; 160 wire [1:0] ExtOp_E; 161 wire [3:0] ALUOp_E; 162 wire [2:0] NPCOp_E; 163 ctrl E_ctrl_P5 ( 164 .Op(IR_E[31:26]), 165 .Func(IR_E[5:0]), 166 .RegDst(RegDst_E), 167 .RegWrite(RegWrite_E), 168 .ALUSrc(ALUSrc_E), 169 .MemWrite(MemWrite_E), 170 .MemtoReg(MemtoReg_E), 171 .ExtOp(ExtOp_E), 172 .ALUOp(ALUOp_E), 173 .NPCOp(NPCOp_E) 174 ); 175 176 //forward 177 wire [31:0] ALU_A; 178 wire [2:0] RSEsel; 179 mux_4_32 MFRSE_P5 ( 180 .a(V1_E), 181 .b(WriteData), 182 .c(PC_M+8), 183 .d(AO_M), 184 .select(RSEsel), 185 .y(ALU_A) 186 ); 187 wire [31:0] ALU_B; 188 wire [2:0] RTEsel; 189 mux_4_32 MFRTE_P5 ( 190 .a(V2_E), 191 .b(WriteData), 192 .c(PC_M+8), 193 .d(AO_M), 194 .select(RTEsel), 195 .y(ALU_B) 196 ); 197 198 wire [31:0] ALU_B_E32; 199 assign ALU_B_E32 = (ALUSrc_E == 0) ? ALU_B : E32_E; 200 //forward 201 202 wire [31:0] ALUOut; 203 wire Zero; 204 ALU ALU_P5 ( 205 .A(ALU_A), 206 .B(ALU_B_E32), 207 .ALUOp(ALUOp_E), 208 .Zero(Zero), 209 .Result(ALUOut) 210 ); 211 212 wire [31:0] IR_M; 213 wire [31:0] V2_M; 214 wire [4:0] WriteReg; 215 mux_3_5 A3_Mux_P5 ( 216 .a(A2_E), 217 .b(A3_E), 218 .c(5‘h1f), 219 .select(RegDst_E), 220 .y(WriteReg) 221 ); 222 223 wire [4:0] A3_M; 224 Reg_M Reg_M_P5 ( 225 .Clock(clk), 226 .Reset(reset), 227 .ALUOut(ALUOut), 228 .ALU_B(ALU_B), 229 .IR_E(IR_E), 230 .PC4_E(PC_E), 231 .A3_E(WriteReg), 232 .IR_M(IR_M), 233 .V2_M(V2_M), 234 .AO_M(AO_M), 235 .A3_M(A3_M), 236 .PC4_M(PC_M) 237 ); 238 //M级 239 240 //M级 241 wire [1:0] RegDst_M; 242 wire RegWrite_M; 243 wire ALUSrc_M; 244 wire MemWrite_M; 245 wire [1:0]MemtoReg_M; 246 wire [1:0] ExtOp_M; 247 wire [3:0] ALUOp_M; 248 wire [2:0] NPCOp_M; 249 ctrl M_ctrl_P5 ( 250 .Op(IR_M[31:26]), 251 .Func(IR_M[5:0]), 252 .RegDst(RegDst_M), 253 .RegWrite(RegWrite_M), 254 .ALUSrc(ALUSrc_M), 255 .MemWrite(MemWrite_M), 256 .MemtoReg(MemtoReg_M), 257 .ExtOp(ExtOp_M), 258 .ALUOp(ALUOp_M), 259 .NPCOp(NPCOp_M) 260 ); 261 262 //forward 263 wire [31:0] WriteData_DM; 264 wire [2:0] RTMsel; 265 assign WriteData_DM = (RTMsel == 1) ? WriteData : V2_M; 266 //forward 267 268 wire [31:0] ReadData_DM; 269 DM DM_P5 ( 270 .Clock(clk), 271 .Reset(reset), 272 .MemWrite(MemWrite_M), 273 .Address(AO_M[11:2]), 274 .WriteData(WriteData_DM), 275 .pc(PC_M), 276 .addr(AO_M), 277 .ReadData(ReadData_DM) 278 ); 279 280 wire [31:0] IR_W; 281 wire [31:0] AO_W; 282 wire [31:0] DR_W; 283 Reg_W Reg_W_P5 ( 284 .Clock(clk), 285 .Reset(reset), 286 .IR_M(IR_M), 287 .A3_M(A3_M), 288 .AO_M(AO_M), 289 .PC4_M(PC_M), 290 .DMOut(ReadData_DM), 291 .IR_W(IR_W), 292 .A3_W(A3_W), 293 .PC4_W(PC_W), 294 .AO_W(AO_W), 295 .DR_W(DR_W) 296 ); 297 //W级 298 299 //W级 300 wire [1:0] RegDst_W; 301 wire ALUSrc_W; 302 wire MemWrite_W; 303 wire [1:0] MemtoReg_W; 304 wire [1:0] ExtOp_W; 305 wire [3:0] ALUOp_W; 306 wire [2:0] NPCOp_W; 307 ctrl W_ctrl_P5 ( 308 .Op(IR_W[31:26]), 309 .Func(IR_W[5:0]), 310 .RegDst(RegDst_W), 311 .RegWrite(RegWrite_W), 312 .ALUSrc(ALUSrc_W), 313 .MemWrite(MemWrite_W), 314 .MemtoReg(MemtoReg_W), 315 .ExtOp(ExtOp_W), 316 .ALUOp(ALUOp_W), 317 .NPCOp(NPCOp_W) 318 ); 319 320 mux_3_32 MemtoReg_Mux_P5 ( 321 .a(AO_W), 322 .b(DR_W), 323 .c(PC_W+8), 324 .select(MemtoReg_W), 325 .y(WriteData) 326 ); 327 //W级 328 329 //冲突 330 Forward Forward_P5 ( 331 .IR_D(IR_D), 332 .IR_E(IR_E), 333 .IR_M(IR_M), 334 .IR_W(IR_W), 335 .RSDsel(RSDsel), 336 .RTDsel(RTDsel), 337 .RSEsel(RSEsel), 338 .RTEsel(RTEsel), 339 .RTMsel(RTMsel) 340 ); 341 342 Stop Stop_P5 ( 343 .IR_D(IR_D), 344 .IR_E(IR_E), 345 .IR_M(IR_M), 346 .Stop(Stop) 347 ); 348 //冲突 349 350 endmodule
1 module PC( 2 input Clock, 3 input Reset, 4 input Stop, 5 input [31:0] NextPC, 6 output reg [31:0] PC 7 ); 8 9 initial begin 10 PC = 32‘h0000_3000; 11 end 12 13 always @ (posedge Clock) begin 14 if(Reset == 1) 15 PC = 32‘h0000_3000; 16 else if(Stop == 1) 17 PC = PC; 18 else 19 PC = NextPC; 20 end 21 22 endmodule
1 module IM( 2 input [9:0] Address, 3 output [31:0] Instr 4 ); 5 6 reg [31:0] memory [1023:0]; 7 integer i; 8 9 initial begin 10 for(i = 0; i < 1024; i = i + 1) 11 memory[i] = 32‘h0; 12 $readmemh("code.txt",memory); 13 end 14 15 assign Instr = memory[Address]; 16 17 endmodule
1 module Reg_D( 2 input Clock, 3 input Reset, 4 input Enable, 5 input [31:0] IR_F, 6 input [31:0] PC_F, 7 output reg [31:0] IR_D, 8 output reg [31:0] NPC_D 9 ); 10 11 initial begin 12 IR_D = 0; 13 NPC_D = 0; 14 end 15 16 always @ (posedge Clock) begin 17 if(Reset == 1) begin 18 IR_D <= 0; 19 NPC_D <= 0; 20 end 21 else if(Enable == 1) begin 22 IR_D <= IR_D; 23 NPC_D <= NPC_D; 24 end 25 else begin 26 IR_D <= IR_F; 27 NPC_D <= PC_F; 28 end 29 end 30 31 endmodule
1 module ctrl( 2 input [5:0] Op, 3 input [5:0] Func, 4 output [1:0] RegDst, 5 output RegWrite, 6 output ALUSrc, 7 output MemWrite, 8 output [1:0]MemtoReg, 9 output [1:0] ExtOp, 10 output [3:0] ALUOp, 11 output [2:0] NPCOp 12 ); 13 initial begin 14 regdst = 2‘b00; 15 regwrite = 0; 16 alusrc = 0; 17 memwrite = 0; 18 memtoreg = 2‘b00; 19 extop = 2‘b00; 20 aluop = 4‘b0000; 21 npcop = 3‘b000; 22 end 23 24 reg [1:0] regdst; 25 reg regwrite; 26 reg alusrc; 27 reg memwrite; 28 reg [1:0] memtoreg; 29 reg [1:0] extop; 30 reg [3:0] aluop; 31 reg [2:0] npcop; 32 33 parameter addu_f = 6‘b100001, 34 subu_f = 6‘b100011, 35 jr_f = 6‘b001000, 36 ori = 6‘b001101, 37 lw = 6‘b100011, 38 sw = 6‘b101011, 39 beq = 6‘b000100, 40 lui = 6‘b001111, 41 j = 6‘b000010, 42 jal = 6‘b000011; 43 44 always @ (Op or Func) begin 45 case(Op) 46 0: begin 47 case(Func) 48 addu_f: begin 49 regdst = 2‘b01; 50 regwrite = 1; 51 alusrc = 0; 52 memwrite = 0; 53 memtoreg = 2‘b00; 54 extop = 2‘bxx; 55 aluop = 4‘b0000; 56 npcop = 3‘b000; 57 end 58 subu_f: begin 59 regdst = 2‘b01; 60 regwrite = 1; 61 alusrc = 0; 62 memwrite = 0; 63 memtoreg = 2‘b00; 64 extop = 2‘bxx; 65 aluop = 4‘b0001; 66 npcop = 3‘b000; 67 end 68 jr_f: begin 69 regdst = 2‘bxx; 70 regwrite = 0; 71 alusrc = 1‘bx; 72 memwrite = 0; 73 memtoreg = 2‘bxx; 74 extop = 2‘bxx; 75 aluop = 4‘bxxxx; 76 npcop = 3‘b011; 77 end 78 default: begin 79 regdst = 2‘b00; 80 regwrite = 0; 81 alusrc = 0; 82 memwrite = 0; 83 memtoreg = 2‘b00; 84 extop = 2‘b00; 85 aluop = 4‘b0000; 86 npcop = 3‘b000; 87 end 88 endcase 89 end 90 ori: begin 91 regdst = 2‘b00; 92 regwrite = 1; 93 alusrc = 1; 94 memwrite = 0; 95 memtoreg = 2‘b00; 96 extop = 2‘b01; 97 aluop = 4‘b0010; 98 npcop = 3‘b000; 99 end 100 lw: begin 101 regdst = 2‘b00; 102 regwrite = 1; 103 alusrc = 1; 104 memwrite = 0; 105 memtoreg = 2‘b01; 106 extop = 2‘b00; 107 aluop = 4‘b0000; 108 npcop = 3‘b000; 109 end 110 sw: begin 111 regdst = 2‘bxx; 112 regwrite = 0; 113 alusrc = 1; 114 memwrite = 1; 115 memtoreg = 2‘bxx; 116 extop = 2‘b00; 117 aluop = 4‘b0000; 118 npcop = 3‘b000; 119 end 120 beq: begin 121 regdst = 2‘bxx; 122 regwrite = 0; 123 alusrc = 0; 124 memwrite = 0; 125 memtoreg = 2‘b00; 126 extop = 2‘b00; 127 aluop = 4‘b0001; 128 npcop = 3‘b001; 129 end 130 lui: begin 131 regdst = 2‘b00; 132 regwrite = 1; 133 alusrc = 1; 134 memwrite = 0; 135 memtoreg = 2‘b00; 136 extop = 2‘b10; 137 aluop = 4‘b0000; 138 npcop = 3‘b000; 139 end 140 jal: begin 141 regdst = 2‘b10; 142 regwrite = 1; 143 alusrc = 1‘bx; 144 memwrite = 0; 145 memtoreg = 2‘b10; 146 extop = 2‘b11; 147 aluop = 4‘b0000; 148 npcop = 3‘b010; 149 end 150 j : begin 151 regdst = 2‘bxx; 152 regwrite = 0; 153 alusrc = 1‘bx; 154 memwrite = 0; 155 memtoreg = 2‘bxx; 156 extop = 2‘bxx; 157 aluop = 4‘bxxxx; 158 npcop = 3‘b010; 159 end 160 endcase 161 end 162 163 assign RegDst = regdst; 164 assign RegWrite = regwrite; 165 assign ALUSrc = alusrc; 166 assign MemWrite = memwrite; 167 assign MemtoReg = memtoreg; 168 assign ExtOp = extop; 169 assign ALUOp = aluop; 170 assign NPCOp = npcop; 171 172 173 endmodule
1 module NPC( 2 input [25:0] Instr, 3 input [31:0] PC_F, 4 input [31:0] PC_D, 5 input [31:0] rs, 6 input [31:0] A, 7 input [31:0] B, 8 input [2:0] NPCOp, 9 output [31:0] npc 10 ); 11 12 wire [15:0] offset; 13 wire [31:0] PC_F4; 14 wire [31:0] PC_D4; 15 wire Zero; 16 parameter other = 3‘b000, 17 beq = 3‘b001, 18 jal_j = 3‘b010, 19 jr = 3‘b011; 20 21 assign offset = Instr[15:0]; 22 assign Zero = (A == B); 23 24 assign PC_F4 = PC_F + 4; 25 assign PC_D4 = PC_D + 4; 26 27 28 assign npc = (NPCOp == other) ? PC_F4 : 29 ((NPCOp == beq) & (Zero == 1)) ? PC_D4 + {{14{offset[15]}},offset,2‘b00} : 30 (NPCOp == jal_j) ? {PC_D[31:28],Instr,2‘b00} : 31 (NPCOp == jr) ? rs : 32 PC_D4 + 4; 33 34 endmodule
1 module GRF( 2 input Clock, 3 input Reset, 4 input RegWrite, 5 input [4:0] ReadReg1, 6 input [4:0] ReadReg2, 7 input [4:0] WriteReg, 8 input [31:0] WriteData, 9 input [31:0] WPC, 10 output [31:0] ReadData1, 11 output [31:0] ReadData2 12 ); 13 14 reg [31:0] register[31:0]; 15 integer i; 16 17 initial begin 18 for(i = 0; i < 32; i = i + 1) 19 register[i] = 0; 20 end 21 22 assign ReadData1 = (ReadReg1 == WriteReg && WriteReg != 0 && RegWrite == 1) ? WriteData : register[ReadReg1]; 23 assign ReadData2 = (ReadReg2 == WriteReg && WriteReg != 0 && RegWrite == 1) ? WriteData : register[ReadReg2]; 24 25 always @ (posedge Clock) begin 26 if(Reset == 1) 27 for(i = 0; i < 32; i = i + 1) 28 register[i] = 32‘h0; 29 else if(RegWrite == 1 && WriteReg != 0) begin 30 register[WriteReg] = WriteData; 31 $display("%[email protected]%h: $%d <= %h", $time, WPC, WriteReg,WriteData); 32 end 33 end 34 35 endmodule
1 module EXT( 2 input [15:0] Imm_16, 3 input [1:0] ExtOp, 4 output [31:0] Imm_32 5 ); 6 7 parameter sign = 2‘b00, 8 zero = 2‘b01, 9 high = 2‘b10, 10 sign_left_2 = 2‘b11; 11 12 assign Imm_32 = (ExtOp == sign) ? {{16{Imm_16[15]}},Imm_16} : 13 (ExtOp == zero) ? {{16‘b0}, Imm_16} : 14 (ExtOp == high) ? {Imm_16,{16‘b0}} : 15 {{14{Imm_16[15]}},Imm_16,2‘b00}; 16 17 endmodule
1 module Reg_E( 2 input Clock, 3 input Reset, 4 input [31:0] IR_D, 5 input [31:0] RF_RD1, 6 input [31:0] RF_RD2, 7 input [31:0] PC4_D, 8 input [31:0] EXT, 9 input [4:0] Rs_IR_D, 10 input [4:0] Rt_IR_D, 11 input [4:0] Rd_IR_D, 12 output reg [31:0] IR_E, 13 output reg [31:0] V1_E, 14 output reg [31:0] V2_E, 15 output reg [4:0] A1_E, 16 output reg [4:0] A2_E, 17 output reg [4:0] A3_E, 18 output reg [31:0] E32_E, 19 output reg [31:0] PC4_E 20 ); 21 22 always @ (posedge Clock) begin 23 if(Reset == 1) begin 24 IR_E <= 0; 25 V1_E <= 0; 26 V2_E <= 0; 27 A1_E <= 0; 28 A2_E <= 0; 29 A3_E <= 0; 30 E32_E <= 0; 31 PC4_E <= 32‘h0000_3000; 32 end 33 else begin 34 IR_E <= IR_D; 35 V1_E <= RF_RD1; 36 V2_E <= RF_RD2; 37 A1_E <= Rs_IR_D; 38 A2_E <= Rt_IR_D; 39 A3_E <= Rd_IR_D; 40 E32_E <= EXT; 41 PC4_E <= PC4_D; 42 end 43 end 44 45 endmodule
1 module ALU( 2 input [31:0] A, 3 input [31:0] B, 4 input [3:0] ALUOp, 5 output Zero, 6 output [31:0] Result 7 ); 8 9 parameter addu = 4‘b0000, 10 subu = 4‘b0001, 11 orr = 4‘b0010; 12 13 assign Result = (ALUOp == addu) ? (A + B) : 14 (ALUOp == subu) ? (A - B) : 15 (A | B); 16 17 assign Zero = (A - B == 0) ? 1 : 0; 18 19 20 endmodule
1 module Reg_M( 2 input Clock, 3 input Reset, 4 input [31:0] ALUOut, 5 input [31:0] ALU_B, 6 input [31:0] IR_E, 7 input [31:0] PC4_E, 8 input [4:0] A3_E, 9 output reg [31:0] IR_M, 10 output reg [31:0] V2_M, 11 output reg [31:0] AO_M, 12 output reg [4:0] A3_M, 13 output reg [31:0] PC4_M 14 ); 15 16 always @ (posedge Clock) begin 17 if(Reset == 1) begin 18 IR_M <= 0; 19 V2_M <= 0; 20 AO_M <= 0; 21 A3_M <= 0; 22 PC4_M <= 32‘h0000_3000; 23 end 24 else begin 25 IR_M <= IR_E; 26 V2_M <= ALU_B; 27 AO_M <= ALUOut; 28 A3_M <= A3_E; 29 PC4_M <= PC4_E; 30 end 31 end 32 33 endmodule
1 module DM( 2 input Clock, 3 input Reset, 4 input MemWrite, 5 input [9:0] Address, 6 input [31:0] WriteData, 7 input [31:0] pc, 8 input [31:0] addr, 9 output[31:0] ReadData 10 ); 11 12 reg [31:0] memory[1023:0]; 13 integer i; 14 15 initial begin 16 for(i = 0; i < 1023; i = i + 1) 17 memory[i] <= 32‘h0; 18 end 19 20 assign ReadData = memory[Address]; 21 22 always @ (posedge Clock) begin 23 if(Reset == 1) 24 for(i = 0; i < 1023; i = i + 1) 25 memory[i] <= 32‘h0; 26 else if(MemWrite == 1) begin 27 memory[Address] = WriteData; 28 $display("%[email protected]%h: *%h <= %h", $time, pc, addr,WriteData); 29 end 30 end 31 32 endmodule
1 module Reg_W( 2 input Clock, 3 input Reset, 4 input [31:0] IR_M, 5 input [4:0] A3_M, 6 input [31:0] AO_M, 7 input [31:0] PC4_M, 8 input [31:0] DMOut, 9 output reg [31:0] IR_W, 10 output reg [4:0] A3_W, 11 output reg [31:0] PC4_W, 12 output reg [31:0] AO_W, 13 output reg [31:0] DR_W 14 ); 15 16 always @ (posedge Clock) begin 17 if(Reset == 1) begin 18 IR_W <= 0; 19 A3_W <= 0; 20 PC4_W <= 32‘h0000_3000; 21 AO_W <= 0; 22 DR_W <= 0; 23 end 24 else begin 25 IR_W <= IR_M; 26 A3_W <= A3_M; 27 PC4_W <= PC4_M; 28 AO_W <= AO_M; 29 DR_W <= DMOut; 30 end 31 end 32 33 endmodule
1 `define opcode 31:26 2 `define func 5:0 3 `define rs 25:21 4 `define rt 20:16 5 `define rd 15:11 6 module Stop( 7 input [31:0] IR_D, 8 input [31:0] IR_E, 9 input [31:0] IR_M, 10 output Stop 11 ); 12 13 parameter R = 6‘b000000, 14 addu_f = 6‘b100001, 15 subu_f = 6‘b100011, 16 jr_f = 6‘b001000, 17 ori = 6‘b001101, 18 lw = 6‘b100011, 19 sw = 6‘b101011, 20 beq = 6‘b000100, 21 lui = 6‘b001111, 22 j = 6‘b000010, 23 jal = 6‘b000011; 24 25 wire b_D, jr_D, cal_r_D, cal_i_D, load_D, store_D; 26 wire cal_r_E, cal_i_E, load_E, store_E; 27 wire load_M; 28 29 wire [4:0] RS_D,RT_D; 30 wire [4:0] RS_E,RT_E,RD_E; 31 wire [4:0] RS_M,RT_M,RD_M; 32 33 wire stall_b_r, stall_b_i, stall_b_load, stall_b_loadM; 34 wire stall_cal_r_load; 35 wire stall_cal_i_load; 36 wire stall_load_load; 37 wire stall_store_load; 38 wire stall_jr_r, stall_jr_i, stall_jr_load, stall_jr_loadM; 39 40 assign {RS_D, RT_D} = {IR_D[`rs], IR_D[`rt]}; 41 assign {RS_E, RT_E, RD_E} = {IR_E[`rs], IR_E[`rt], IR_E[`rd]}; 42 assign {RS_M, RT_M, RD_M} = {IR_M[`rs], IR_M[`rt], IR_M[`rd]}; 43 44 assign b_D = (IR_D[`opcode] == beq); 45 assign jr_D = (IR_D[`opcode] == R) & (IR_D[`func] == jr_f); 46 assign cal_r_D = (IR_D[`opcode] == R) & (IR_D[`func] != jr_f); 47 assign cal_i_D = (IR_D[`opcode] == ori) | (IR_D[`opcode] == lui); 48 assign load_D = (IR_D[`opcode] == lw); 49 assign store_D = (IR_D[`opcode] == sw); 50 51 assign cal_r_E = (IR_E[`opcode] == R) & (IR_E[`func] != jr_f); 52 assign cal_i_E = (IR_E[`opcode] == ori) | (IR_E[`opcode] == lui); 53 assign load_E = (IR_E[`opcode] == lw); 54 assign store_E = (IR_E[`opcode] == sw); 55 56 assign load_M = (IR_M[`opcode] == lw); 57 58 assign stall_b_r = b_D & cal_r_E & ( (RS_D == RD_E) | (RT_D == RD_E) ); 59 assign stall_b_i = b_D & cal_i_E & ( (RS_D == RT_E) | (RT_D == RT_E) ); 60 assign stall_b_load = b_D & load_E & ( (RS_D == RT_E) | (RT_D == RT_E) ); 61 assign stall_b_loadM = b_D & load_M & ( (RS_D == RT_M) | (RT_D == RT_M) ); 62 63 assign stall_cal_r_load = cal_r_D & load_E & ( (RS_D == RT_E) | (RT_D == RT_E) ); 64 65 assign stall_cal_i_load = cal_i_D & load_E & (RS_D == RT_E); 66 67 assign stall_load_load = load_D & load_E & (RS_D == RT_E); 68 69 assign stall_store_load = store_D & load_E & (RS_D == RT_E); 70 71 assign stall_jr_r = jr_D & cal_r_E & (RS_D == RD_E); 72 assign stall_jr_i = jr_D & cal_i_E & (RS_D == RT_E); 73 assign stall_jr_load = jr_D & load_E & (RS_D == RT_E); 74 assign stall_jr_loadM = jr_D & load_M & (RS_D == RT_M); 75 76 assign Stop = stall_b_r | stall_b_i | stall_b_load | stall_b_loadM | 77 stall_cal_r_load | stall_cal_i_load | 78 stall_load_load | stall_store_load | 79 stall_jr_r | stall_jr_i | stall_jr_load | stall_jr_loadM; 80 81 endmodule
1 `define opcode 31:26 2 `define func 5:0 3 `define rs 25:21 4 `define rt 20:16 5 `define rd 15:11 6 module Forward( 7 input [31:0] IR_D, 8 input [31:0] IR_E, 9 input [31:0] IR_M, 10 input [31:0] IR_W, 11 output [2:0] RSDsel, 12 output [2:0] RTDsel, 13 output [2:0] RSEsel, 14 output [2:0] RTEsel, 15 output [2:0] RTMsel 16 ); 17 18 parameter R = 6‘b000000, 19 addu_f = 6‘b100001, 20 subu_f = 6‘b100011, 21 jr_f = 6‘b001000, 22 ori = 6‘b001101, 23 lw = 6‘b100011, 24 sw = 6‘b101011, 25 beq = 6‘b000100, 26 lui = 6‘b001111, 27 j = 6‘b000010, 28 jal = 6‘b000011; 29 30 wire b_D, jr_D; 31 wire cal_r_E, cal_i_E, jal_E,load_E, store_E; 32 wire cal_r_M, cal_i_M, jal_M,load_M, store_M; 33 wire cal_r_W, cal_i_W, jal_W,load_W, store_W; 34 35 wire [4:0] RS_D,RT_D; 36 wire [4:0] RS_E,RT_E,RD_E; 37 wire [4:0] RS_M,RT_M,RD_M; 38 wire [4:0] RS_W,RT_W,RD_W; 39 40 assign {RS_D, RT_D} = {IR_D[`rs], IR_D[`rt]}; 41 assign {RS_E, RT_E, RD_E} = {IR_E[`rs], IR_E[`rt], IR_E[`rd]}; 42 assign {RS_M, RT_M, RD_M} = {IR_M[`rs], IR_M[`rt], IR_M[`rd]}; 43 assign {RS_W, RT_W, RD_W} = {IR_W[`rs], IR_W[`rt], IR_W[`rd]}; 44 45 assign b_D = (IR_D[`opcode] == beq); 46 assign jr_D = (IR_D[`opcode] == R) & (IR_D[`func] == jr_f); 47 48 assign cal_r_E = (IR_E[`opcode] == R) & (IR_E[`func] != jr_f); 49 assign cal_i_E = (IR_E[`opcode] == ori) | (IR_E[`opcode] == lui); 50 assign jal_E = (IR_E[`opcode] == jal); 51 assign load_E = (IR_E[`opcode] == lw); 52 assign store_E = (IR_E[`opcode] == sw); 53 54 assign cal_r_M = (IR_M[`opcode] == R) & (IR_M[`func] != jr_f); 55 assign cal_i_M = (IR_M[`opcode] == ori) | (IR_M[`opcode] == lui); 56 assign jal_M = (IR_M[`opcode] == jal); 57 assign load_M = (IR_M[`opcode] == lw); 58 assign store_M = (IR_M[`opcode] == sw); 59 60 assign cal_r_W = (IR_W[`opcode] == R) & (IR_W[`func] != jr_f); 61 assign cal_i_W = (IR_W[`opcode] == ori) | (IR_W[`opcode] == lui); 62 assign jal_W = (IR_W[`opcode] == jal); 63 assign load_W = (IR_W[`opcode] == lw); 64 assign store_W = (IR_W[`opcode] == sw); 65 66 67 assign RSDsel = ( (b_D | jr_D) & jal_E & (RS_D == 31) ) ? 4 : 68 ( (b_D | jr_D) & cal_r_M & (RS_D == RD_M) & (RS_D != 0) ) ? 3 : 69 ( (b_D | jr_D) & cal_i_M & (RS_D == RT_M) & (RS_D != 0) ) ? 3 : 70 ( (b_D | jr_D) & jal_M & (RS_D == 31) ) ? 2 : 71 ( (b_D | jr_D) & cal_r_W & (RS_D == RD_W) & (RS_D != 0) ) ? 1 : 72 ( (b_D | jr_D) & cal_i_W & (RS_D == RT_W) & (RS_D != 0) ) ? 1 : 73 ( (b_D | jr_D) & load_W & (RS_D == RT_W) & (RS_D != 0) ) ? 1 : 74 ( (b_D | jr_D) & jal_W & (RS_D == 31) ) ? 1 : 75 0; 76 77 assign RTDsel = ( b_D & jal_E & (RT_D == 31) ) ? 4 : 78 ( b_D & cal_r_M & (RT_D == RD_M) & (RT_D != 0) ) ? 3 : 79 ( b_D & cal_i_M & (RT_D == RT_M) & (RT_D != 0) ) ? 3 : 80 ( b_D & jal_M & (RT_D == 31) ) ? 2 : 81 ( b_D & cal_r_W & (RT_D == RD_W) & (RT_D != 0) ) ? 1 : 82 ( b_D & cal_i_W & (RT_D == RT_W) & (RT_D != 0) ) ? 1 : 83 ( b_D & load_W & (RT_D == RT_W) & (RT_D != 0) ) ? 1 : 84 ( b_D & jal_W & (RT_D == 31) ) ? 1 : 85 0; 86 87 assign RSEsel = ( (cal_r_E | cal_i_E | load_E | store_E) & cal_r_M & (RS_E == RD_M) & (RS_E != 0) ) ? 3 : 88 ( (cal_r_E | cal_i_E | load_E | store_E) & cal_i_M & (RS_E == RT_M) & (RS_E != 0) ) ? 3 : 89 ( (cal_r_E | cal_i_E | load_E | store_E) & jal_M & (RS_E == 31) ) ? 2 : 90 ( (cal_r_E | cal_i_E | load_E | store_E) & cal_r_W & (RS_E == RD_W) & (RS_E != 0) ) ? 1 : 91 ( (cal_r_E | cal_i_E | load_E | store_E) & cal_i_W & (RS_E == RT_W) & (RS_E != 0) ) ? 1 : 92 ( (cal_r_E | cal_i_E | load_E | store_E) & load_W & (RS_E == RT_W) & (RS_E != 0) ) ? 1 : 93 ( (cal_r_E | cal_i_E | load_E | store_E) & jal_W & (RS_E == 31) ) ? 1 : 94 0; 95 96 assign RTEsel = ( (cal_r_E | store_E) & cal_r_M & (RT_E == RD_M) & (RT_E != 0) ) ? 3 : 97 ( (cal_r_E | store_E) & cal_i_M & (RT_E == RT_M) & (RT_E != 0) ) ? 3 : 98 ( (cal_r_E | store_E) & jal_M & (RT_E == 31) ) ? 2 : 99 ( (cal_r_E | store_E) & cal_r_W & (RT_E == RD_W) & (RT_E != 0) ) ? 1 : 100 ( (cal_r_E | store_E) & cal_i_W & (RT_E == RT_W) & (RT_E != 0) ) ? 1 : 101 ( (cal_r_E | store_E) & load_W & (RT_E == RT_W) & (RT_E != 0) ) ? 1 : 102 ( (cal_r_E | store_E) & jal_W & (RT_E == 31) ) ? 1 : 103 0; 104 assign RTMsel = ( store_M & cal_r_W & (RT_M == RD_W) & (RT_M != 0) ) ? 1 : 105 ( store_M & cal_i_W & (RT_M == RT_W) & (RT_M != 0) ) ? 1 : 106 ( store_M & load_W & (RT_M == RT_W) & (RT_M != 0) ) ? 1 : 107 ( store_M & jal_W & (RT_M == 31) ) ? 1 : 108 0; 109 110 endmodule
1 module mux_3_5( 2 input [4:0] a,b,c, 3 input [1:0] select, 4 output [4:0] y 5 ); 6 7 assign y = (select == 0) ? a : 8 (select == 1) ? b : 9 c; 10 endmodule 11 12 module mux_3_32( 13 input [31:0] a,b,c, 14 input [1:0] select, 15 output [31:0] y 16 ); 17 18 assign y = (select == 0) ? a : 19 (select == 1) ? b : 20 c; 21 endmodule 22 23 module mux_4_32( 24 input [31:0] a,b,c,d, 25 input [2:0] select, 26 output [31:0] y 27 ); 28 29 assign y = (select == 0) ? a : 30 (select == 1) ? b : 31 (select == 2) ? c : 32 d; 33 endmodule 34 35 module mux_5_32( 36 input [31:0] a,b,c,d,e, 37 input [2:0] select, 38 output [31:0] y 39 ); 40 41 assign y = (select == 0) ? a : 42 (select == 1) ? b : 43 (select == 2) ? c : 44 (select == 3) ? d : 45 e; 46 47 endmodule
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