Xilinx ISE错误 “MapLib:30 - LOC constraint......”
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Using target part "2vp30fg676-7".
Mapping design into LUTs...
ERROR:MapLib:30 - LOC constraint AJ15 on clk is invalid: No such site on the
device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint AG15 on jtag_tck is invalid: No such site on
the device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint AG16 on jtag_tdo is invalid: No such site on
the device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint AJ16 on jtag_tms is invalid: No such site on
the device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint AC4 on oLED<0> is invalid: No such site on the
device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint AH5 on rstn is invalid: No such site on the
device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint AJ8 on uart_srx is invalid: No such site on the
device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
ERROR:MapLib:30 - LOC constraint AE7 on uart_stx is invalid: No such site on the
device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.
Error found in mapping process, exiting...
Errors found during the mapping phase. Please see map report file for more
details. Output files will not be written.
Design Summary
--------------
Number of errors : 8
Number of warnings : 2
Process "Map" failed
??
Xilinx_ISE 14.7 Win10 闪退
打开D:Xilinx14.7ISE_DSISElib
t64
将libPortabilityNOSH.dll 重命名为libPortability.dll,替换原libPortability.dll
并且复制到D:Xilinx14.7ISE_DScommonlib
t64下替换原libPortability.dll
https://blog.csdn.net/idevede/article/details/56024153
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