在 VHDL 中，如何将输出端口列表分配给数组？

Posted 2023-02-22

【中文标题】在 VHDL 中，如何将输出端口列表分配给数组？

【英文标题】：in VHDL, how to assign list of output ports to an array?

【发布时间】：2018-02-14 04:45:46

【问题描述】：

我有一个具有数百个输出的实体，例如 tap0(15 downto 0)、tap1(15 downto 0)、...、tap200(15 downto 0)

对于每次迭代，我想将其中四个输出分配给具有四个输入的复数乘法器实体。

例如： 第一次迭代：

mult_in_A <= tap0;
mult_in_B <= tap1;
mult_in_C <= tap2;
mult_in_D <= tap3;

第二次迭代：

mult_in_A <= tap4;
mult_in_B <= tap5;
mult_in_C <= tap6;
mult_in_D <= tap7;

第三次迭代：

mult_in_A <= tap8;
mult_in_B <= tap9;
mult_in_C <= tap10;
mult_in_D <= tap11;

等等……

如何通过某种 for 循环并将这些输出端口放入数组来提高上述代码的效率？这样我就可以编写如下代码：

mult_in_A <= tap_array(i);
mult_in_A <= tap_array(i+1);
mult_in_A <= tap_array(i+2);
mult_in_A <= tap_array(i+3);

更新：

这是代码示例

ARCHITECTURE rtl_syn OF fir_filter_cntl IS

COMPONENT delay_line
PORT(
    aclr        : IN STD_LOGIC;
    clock       : IN STD_LOGIC;
    clken       : IN STD_LOGIC;
    shiftin     : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
    shiftout    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
    taps0x      : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
    taps1x      : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
    taps2x      : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
    taps3x      : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
    ...
    taps128x    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
    taps129x    : OUT STD_LOGIC_VECTOR (15 DOWNTO 0));
END COMPONENT;

TYPE samples IS array (0 to 129) of std_logic_vector(15 downto 0);
SIGNAL sample_i: samples;

BEGIN

delay_line_i1 : delay_line
    PORT MAP (
    aclr        => rx_reset,
    clock       => rx_clock,
    clken       => i_clken,
    shiftin     => i_sample,
    shiftout    => open,
    taps0x      => sample_i(0),  -- <- this doesn't work. In simulation,
                                 -- I observed taps0x output has some valid
                                 -- values, but sample_i's value is unknown
    taps1x      => sample_i(1),
    taps2x      => sample_i(2),
    ...
    taps129x    => sample_i(129));

然后在下面的某些过程中，我有以下内容：

sample_counter      <= (others => '0');

CASE device_number IS
    WHEN "000" =>
        complex_mult_0I_in  <= sample_i(conv_integer(sample_counter+0)); 
        complex_mult_1I_in  <= sample_i(conv_integer(sample_counter+1));
        complex_mult_2I_in  <= sample_i(conv_integer(sample_counter+2));
        complex_mult_3I_in  <= sample_i(conv_integer(sample_counter+3));

几个问题： 1. 为什么下面的端口分配有效？ taps0x => sample_i(0) 2. 如何使用 for..loop 或 for..generate 来简化以下代码？

taps0x => sample_i(0),
taps1x => sample_i(1), 
taps2x => sample_i(2),
taps3x => sample_i(3),
taps4x => sample_i(4), 
taps5x => sample_i(5),
and so on.

【问题讨论】：

是的，你可以。查找for loops 和for generates

您需要展示您为尝试解决此问题而编写的代码，并说明您遇到的问题或错误。

@scary_jeff 我喜欢this 网站的这种反馈。例如：idownvotedbecau.se/noattempt

您的编辑对于您之前的问题毫无意义，而且它不完整。您似乎在问两个问题。

【参考方案1】：

嗯，sample 类型你做得很好...那么为什么不在界面上使用它呢？

示例：

-- custom package
library ieee;

package custom_types is
    use ieee.std_logic_1164.all;
    type std_logic_vector_vector is array (natural range <>) of std_logic_vector;
end package;

-- your component... simplified
library ieee;
use ieee.std_logic_1164.all;
use work.custom_types.all;

entity delay_line is
    port(
        -- note: 130 does not divide by 4
        tapsx : out std_logic_vector_vector(0 to 127)(15 downto 0)
    );
end entity;

architecture empty of delay_line is begin end architecture;

-- some entity using your component
entity use_delay_line is end entity;

library ieee;

architecture rtl of use_delay_line is
    use work.custom_types.all;
    signal tapsx : std_logic_vector_vector(0 to 127)(15 downto 0);
    use ieee.std_logic_1164.all;
    signal mult_a, mult_b, mult_c, mult_d : std_logic_vector(15 downto 0);
begin
    delay_line_inst : entity work.delay_line
        port map(
            tapsx => tapsx
            );

    process
    begin
        for it in 0 to 31 loop
            mult_a <= tapsx(it*4);
            mult_b <= tapsx(it*4+1);
            mult_c <= tapsx(it*4+2);
            mult_d <= tapsx(it*4+3);
            wait for 10 ns;
        end loop;
        wait;
    end process;
end architecture;