具有 Mux 8:3 的 VHDL 全加器

Posted 2023-02-25

【中文标题】具有 Mux 8:3 的 VHDL 全加器

【英文标题】：VHDL Full adder with Mux 8:3

【发布时间】：2012-01-02 18:25:19

【问题描述】：

我尝试使用 Mux8:3 创建一个全加器...但它没有运行！ 当我运行它时，我没有从命令行收到任何错误，但是 ghdl 没有启动！ 有人可以阅读这段代码并告诉我该怎么做吗？

              -----------------------MUX8ingressi-------------------
        library IEEE;
        use IEEE.std_logic_1164.all;

        entity mux8 is 
          port(
               A: in STD_LOGIC;
               B: in STD_LOGIC; 
               C: in STD_LOGIC;
               D: in STD_LOGIC; 
               E: in STD_LOGIC;
               F: in STD_LOGIC;
               G: in STD_LOGIC;
               H: in STD_LOGIC;
               S1: in STD_LOGIC;
               S2: in STD_LOGIC;
               S3: in STD_LOGIC;
               U: out STD_LOGIC 
          );
        end mux8;


        architecture RTL of mux8 is 
        signal S: STD_LOGIC_VECTOR (2 downto 0);

          begin
            S <= S1&S2&S3;
            U <= A when S="000" else
                 B when S="001" else
                 C when S="010" else
                 D when S="011" else
                 E when S="100" else
                 F when S="101" else
                 G when S="110" else
                 H;
                 
          end RTL;
          
        -------------------FULL ADDER-------------------------------
        library IEEE;
        use IEEE.std_logic_1164.all;

        entity FA is 
          port(
               add1: in STD_LOGIC; 
               add2: in STD_LOGIC; 
               Ci: in STD_LOGIC;
               S: out STD_LOGIC;
               Co: out STD_LOGIC
          );
        end FA;

        architecture RTL of FA is 
        --  Ci  A  B |  Co  S
        -------------|---------
        --   0  0  0 |   0  0
        --   0  0  1 |   0  1
        --   0  1  0 |   0  1
        --   0  1  1 |   1  0
        --   1  0  0 |   0  1
        --   1  0  1 |   1  0
        --   1  1  0 |   1  0 
        --   1  1  1 |   1  1

        component mux8 is
          port(
               A: in STD_LOGIC; 
               B: in STD_LOGIC;
               C: in STD_LOGIC; 
               D: in STD_LOGIC;
               E: in STD_LOGIC;
               F: in STD_LOGIC;
               G: in STD_LOGIC;
               H: in STD_LOGIC;
               S1: in STD_LOGIC;
               S2: in STD_LOGIC;
               S3: in STD_LOGIC;
               U: out STD_LOGIC
          );
        end component;

          begin
            test: mux8 port map (
                                    A=>'0',
                                    B=>'1',
                                    C=>'1',
                                    D=>'0',
                                    E=>'1',
                                    F=>'0',
                                    G=>'0',
                                    H=>'1',
                                    S1=>add1,
                                    S2=>add2,
                                    S3=>Ci,
                                    U=>S
                                    );
            
          end RTL;
         
        -----------------TEST BENCH-----------------
        library IEEE;
        use IEEE.std_logic_1164.all;

        entity FA_tb is 
        end FA_tb;


        architecture test of FA_tb is 
        component FA is 
          port(
               add1: in STD_LOGIC; 
               add2: in STD_LOGIC; 
               Ci: in STD_LOGIC;
               S: out STD_LOGIC; 
               Co: out STD_LOGIC
          );
        end component;

        signal add1_tb, add2_tb, Ci_tb, S_tb, Co_tb: STD_LOGIC;
        signal  ideal_co: STD_LOGIC; 
        signal  ideal_s: STD_LOGIC;
        signal  ERRORE_S,ERRORE_Co: STD_LOGIC := '0'; 

        begin 

            UUT: FA port map (add1=>add1_tb, add2=>add2_tb, Ci=>Ci_tb, S=>S_tb, Co=>Co_tb);

            process
            begin
            add1_tb<='0'; add2_tb<='0'; Ci_tb<='0'; ideal_co<='0'; ideal_s<='0';
            wait for 10 ns;
            add1_tb<='0'; add2_tb<='1'; Ci_tb<='0'; ideal_co<='0'; ideal_s<='1';
            wait for 10 ns;
            add1_tb<='1'; add2_tb<='0'; Ci_tb<='0'; ideal_co<='0'; ideal_s<='1';
            wait for 10 ns;
            add1_tb<='1'; add2_tb<='1'; Ci_tb<='0'; ideal_co<='1'; ideal_s<='0';
            wait for 10 ns;
            add1_tb<='0'; add2_tb<='0'; Ci_tb<='1'; ideal_co<='0'; ideal_s<='1';
            wait for 10 ns;
            add1_tb<='0'; add2_tb<='1'; Ci_tb<='1'; ideal_co<='1'; ideal_s<='0';
            wait for 10 ns;
            add1_tb<='1'; add2_tb<='0'; Ci_tb<='1'; ideal_co<='1'; ideal_s<='0';
            wait for 10 ns;
            add1_tb<='1'; add2_tb<='1'; Ci_tb<='1'; ideal_co<='1'; ideal_s<='1';
            wait for 10 ns;
            
            wait;
            end process;
          
        end test;

现在是我的 make.bat

    echo off
    cls
    set path=%path%;C:\Program files\GHDL\bin;C:\Program files\GHDL\gtk\bin;

    echo on
    ghdl -a FAconMUX_83.vhdl
    ghdl -e mux8
    ghdl -e FA
    ghdl -e FA_tb
    ghdl -r FA_tb --vcd=out83.vcd
    gtkwave out83.vcd

【问题讨论】：

您能否更新您的问题以包含您用于编译、详细说明和运行模拟的命令？

我在 Linux 上的 ghdl 中尝试了你的代码，它分析、编译和运行正常。我没有在 gtkwave 中检查 VCD 文件，但生成了一个 VCD 文件，它确实包含一些活动。您应该检查您的 ghdl 安装，这可能是这里的错误。

【参考方案1】：

您的代码编译得很好，我在 Windows 8 上使用 Altera Quartus II 14.0 进行了尝试。我建议您使用其他综合工具，或者只使用逻辑门来获得求和和进位。 最好的祝福