如何修复 Verilator 的凿子测试错误（应该与 verilator 一起使用 *** FAILED ***）？

Posted 2023-02-23

【中文标题】如何修复 Verilator 的凿子测试错误（应该与 verilator 一起使用 *** FAILED ***）？

【英文标题】：How to fix chisel test errors whit Verilator (should work with verilator *** FAILED ***)?

【发布时间】：2019-09-27 13:31:37

【问题描述】：

我运行凿子测试并希望使用验证器生成输出。我无法准确找到错误的原因，但我认为这与验证器有关。 这是执行测试的代码部分。它必须打印一些输出并生成模拟文件。

class ComplexMemoryLoadingSpec extends  FreeSpec with Matchers 
  "memory loading should be possible with complex memories" - 

    val targetDirName = "test_run_dir/complex_mem_test"
    FileUtils.makeDirectory(targetDirName)

    val path1 = Paths.get(targetDirName + "/mem_cameraman.bin")


    Files.copy(getClass.getResourceAsStream("/cameraman.bin"), path1, REPLACE_EXISTING)



    "should work with verilator" in 
      iotesters.Driver.execute(
        args = Array("--backend-name", "verilator", "--target-dir", targetDirName, "--top-name", "complex_mem_test"),
        dut = () => new HasComplexMemory(memoryDepth = 65536)
      )  c =>
        new HasComplexMemoryTester(c)
       should be(true)
    
  

它不起作用，我收到了这个错误：

[info] Done compiling.
[info] [0.005] Elaborating design...
[info] [0.515] Done elaborating.
Total FIRRTL Compile Time: 1965.5 ms
cd /home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test && verilator --cc HasComplexMemory.v --assert -Wno-fatal -Wno-WIDTH -Wno-STMTDLY -O1 --top-module HasComplexMemory +define+TOP_TYPE=VHasComplexMemory +define+PRINTF_COND=!HasComplexMemory.reset +define+STOP_COND=!HasComplexMemory.reset -CFLAGS "-Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VHasComplexMemory -DVL_USER_FINISH -include VHasComplexMemory.h" -Mdir /home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test -f /home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test/firrtl_black_box_resource_files.f --exe /home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test/HasComplexMemory-harness.cpp --trace
make: Entering directory '/home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test'
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VHasComplexMemory -DVL_USER_FINISH -include VHasComplexMemory.h   -c -o HasComplexMemory-harness.o /home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test/HasComplexMemory-harness.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VHasComplexMemory -DVL_USER_FINISH -include VHasComplexMemory.h   -c -o verilated.o /usr/local/share/verilator/include/verilated.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VHasComplexMemory -DVL_USER_FINISH -include VHasComplexMemory.h   -c -o verilated_vcd_c.o /usr/local/share/verilator/include/verilated_vcd_c.cpp
/usr/bin/perl /usr/local/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VHasComplexMemory.cpp VHasComplexMemory___024unit.cpp > VHasComplexMemory__ALLcls.cpp
/usr/bin/perl /usr/local/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include VHasComplexMemory__Trace.cpp VHasComplexMemory__Syms.cpp VHasComplexMemory__Trace__Slow.cpp > VHasComplexMemory__ALLsup.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VHasComplexMemory -DVL_USER_FINISH -include VHasComplexMemory.h   -c -o VHasComplexMemory__ALLcls.o VHasComplexMemory__ALLcls.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow     -Wno-undefined-bool-conversion -O1 -DTOP_TYPE=VHasComplexMemory -DVL_USER_FINISH -include VHasComplexMemory.h   -c -o VHasComplexMemory__ALLsup.o VHasComplexMemory__ALLsup.cpp
      Archiving VHasComplexMemory__ALL.a ...
ar r VHasComplexMemory__ALL.a VHasComplexMemory__ALLcls.o VHasComplexMemory__ALLsup.o
ranlib VHasComplexMemory__ALL.a
g++    HasComplexMemory-harness.o verilated.o verilated_vcd_c.o VHasComplexMemory__ALL.a    -o VHasComplexMemory -lm -lstdc++ 
make: Leaving directory '/home/med/workspace/ChiselProjects/convolution/test_run_dir/complex_mem_test'
sim start on Dell at Fri Sep 27 13:38:29 2019
inChannelName: 00008431.in
outChannelName: 00008431.out
cmdChannelName: 00008431.cmd
STARTING test_run_dir/complex_mem_test/VHasComplexMemory
Enabling waves..%Error: test_run_dir/complex_mem_test/mem_a:0: $readmem file not found
Aborting...
[info] ComplexMemoryLoadingSpec:
[info] memory loading should be possible with complex memories
[info] - should work with verilator *** FAILED ***
[info]   chisel3.iotesters.TestApplicationException: test application exit - exit code 134
[info]   at chisel3.iotesters.SimApiInterface.throwExceptionIfDead(SimApiInterface.scala:98)
[info]   at chisel3.iotesters.SimApiInterface.chisel3$iotesters$SimApiInterface$$mwhile(SimApiInterface.scala:107)
[info]   at chisel3.iotesters.SimApiInterface$$anonfun$start$3.apply$mcVI$sp(SimApiInterface.scala:268)
[info]   at scala.collection.immutable.Range.foreach$mVc$sp(Range.scala:160)
[info]   at chisel3.iotesters.SimApiInterface.start(SimApiInterface.scala:266)
[info]   at chisel3.iotesters.SimApiInterface.<init>(SimApiInterface.scala:325)
[info]   at chisel3.iotesters.VerilatorBackend.<init>(VerilatorBackend.scala:295)
[info]   at chisel3.iotesters.setupVerilatorBackend$.apply(VerilatorBackend.scala:284)
[info]   at chisel3.iotesters.Driver$$anonfun$execute$1$$anonfun$apply$mcZ$sp$1.apply$mcZ$sp(Driver.scala:56)
[info]   at chisel3.iotesters.Driver$$anonfun$execute$1$$anonfun$apply$mcZ$sp$1.apply(Driver.scala:39)
[info]   ...
[info] ScalaTest
[info] Run completed in 1 minute, 41 seconds.
[info] Total number of tests run: 1
[info] Suites: completed 1, aborted 0
[info] Tests: succeeded 0, failed 1, canceled 0, ignored 0, pending 0
[info] *** 1 TEST FAILED ***
[error] Failed: Total 1, Failed 1, Errors 0, Passed 0
[error] Failed tests:
[error]     util.ComplexMemoryLoadingSpec
[error] (Test / testOnly) sbt.TestsFailedException: Tests unsuccessful

有人可以帮助我吗？或解释那里出了什么问题

【参考方案1】：

我认为问题在于它找不到包含您要加载到内存中的数据的文件。如果它是一个复杂的内存，那么您需要为内存中的每个不同项目创建一个单独的文件。

找不到文件test_run_dir/complex_mem_test/mem_a 我猜这两行

val path1 = Paths.get(targetDirName + "/mem_cameraman.bin")
Files.copy(getClass.getResourceAsStream("/cameraman.bin"), path1,REPLACE_EXISTING)

正在尝试将数据文件放在 verilator 可以找到它的位置，但我认为这与代码所说的文件将被找到的位置不匹配。

你能显示内存声明和你指定文件名的位置吗？ 这肯定很复杂。在loading chisel memories查看此文档

【讨论】：

你好，我做了一些修改，终于找到了文件，但是出现了一个新的错误%Error: test_run_dir/complex_mem_test/cameraman_a:1: $readmem file syntax error我猜是文件格式有问题。

我在github上发布了代码，这里是查看的链接Test Failed with chisel-testers

我已经在您创建的问题中回答了您的问题。在我看来，您的文件位置确实正确，但其内容可能存在问题