BT1120时序，可以用于自测度
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module bt1120_gen #( parameter H_SYNC = 44, parameter H_FRONT_PORCH = 88, parameter H_BACK_PORCH = 148, parameter V_SYNC = 5, parameter V_FRONT_PORCH = 4, parameter V_BACK_PORCH = 36 )( input clk, input rst_p, // input [5:0] h_sync_pixcels, // input [5:0] h_front_porch_pixcels, // input [5:0] h_back_porch_pixcels, // input [5:0] v_sync_lines, // input [5:0] v_front_porch_lines, // input [5:0] v_back_porch_lines, input [12:0] col, input [12:0] row, output reg[15:0] odata, output reg v_sync, output reg h_sync, output reg de ); parameter S_H_SYNC = 2‘b00; parameter S_H_BACK_PORCH = 2‘b01; parameter S_H_ACTIVE = 2‘b10; parameter S_H_FRONT_PORCH = 2‘b11; parameter S_V_SYNC = 2‘b00; parameter S_V_BACK_PORCH = 2‘b01; parameter S_V_ACTIVE = 2‘b10; parameter S_V_FRONT_PORCH = 2‘b11; reg [1:0] h_pre_state = S_H_FRONT_PORCH; reg [1:0] h_nx_state = S_H_FRONT_PORCH; reg [1:0] v_pre_state = S_V_SYNC; reg [1:0] v_nx_state = S_V_SYNC; reg [12:0] h_cnt = 0; reg [12:0] v_cnt = 0; reg [15:0] sync_code = 0; reg de_r = 1‘b0; reg vid_sop_r = 1‘b0; wire pos_vid_sop; reg fifo_rd_valid = 1‘b0; reg [15:0] fifo_rd_data_r = 16‘d0; reg [15:0] sync_code_r = 16‘d0; reg [15:0] sync_code_r1 = 16‘d0; reg de_r1 = 1‘b0; reg de_r2 = 1‘b0; reg h_sync_r = 1‘b0; reg h_sync_r1 = 1‘b0; reg h_sync_r2 = 1‘b0; reg v_sync_r = 1‘b0; reg v_sync_r1 = 1‘b0; reg v_sync_r2 = 1‘b0; reg data_en = 1‘b0; reg data_en_dly = 1‘b0; always @( posedge clk ) begin if( h_nx_state == S_H_ACTIVE && v_nx_state == S_V_ACTIVE ) data_en <= 1‘b1; else data_en <= 1‘b0; end always @( posedge clk ) begin data_en_dly <= data_en; end always @( posedge clk ) begin if( data_en_dly ) fifo_rd_data_r <= fifo_rd_data_r + 1‘b1; else fifo_rd_data_r <= 16‘d0; end /*********************************************************************** ***********************************************************************/ always @( posedge clk )//or posedge rst_p begin if( rst_p ) begin h_pre_state <= S_H_FRONT_PORCH; v_pre_state <= S_V_SYNC; end else begin h_pre_state <= h_nx_state; v_pre_state <= v_nx_state; end end always @( * ) begin case( h_pre_state ) S_H_SYNC : if( h_cnt == H_SYNC -1 ) h_nx_state <= S_H_BACK_PORCH; else h_nx_state <= S_H_SYNC; S_H_BACK_PORCH : begin if( h_cnt == H_BACK_PORCH -1 ) h_nx_state <= S_H_ACTIVE; else h_nx_state <= S_H_BACK_PORCH; end S_H_ACTIVE : begin if( h_cnt == col -1 ) h_nx_state <= S_H_FRONT_PORCH; else h_nx_state <= S_H_ACTIVE; end S_H_FRONT_PORCH : begin if( h_cnt == H_FRONT_PORCH -1 ) h_nx_state <= S_H_SYNC; else h_nx_state <= S_H_FRONT_PORCH; end default:; endcase end always @( * ) begin case( v_pre_state ) S_V_SYNC : begin if( h_nx_state == S_H_FRONT_PORCH && h_pre_state == S_H_ACTIVE ) begin if( v_cnt == V_SYNC -1 ) v_nx_state = S_V_BACK_PORCH; else v_nx_state = S_V_SYNC; end else begin v_nx_state = S_V_SYNC; end end S_V_BACK_PORCH : begin if( h_nx_state == S_H_FRONT_PORCH && h_pre_state == S_H_ACTIVE ) begin if( v_cnt == V_BACK_PORCH -1 ) v_nx_state = S_V_ACTIVE; else v_nx_state = S_V_BACK_PORCH; end else begin v_nx_state = S_V_BACK_PORCH; end end S_V_ACTIVE : begin if( h_nx_state == S_H_FRONT_PORCH && h_pre_state == S_H_ACTIVE ) begin if( v_cnt == row -1 ) v_nx_state = S_V_FRONT_PORCH; else v_nx_state = S_V_ACTIVE; end else begin v_nx_state = S_V_ACTIVE; end end S_V_FRONT_PORCH : begin if( h_nx_state == S_H_FRONT_PORCH && h_pre_state == S_H_ACTIVE ) begin if( v_cnt == V_FRONT_PORCH -1‘b1 ) v_nx_state = S_V_SYNC; else v_nx_state = S_V_FRONT_PORCH; end else begin v_nx_state = S_V_FRONT_PORCH; end end default:; endcase // end else begin // v_nx_state = v_nx_state; // end // end /*********************************************************************** cnt ***********************************************************************/ always @( posedge clk ) begin if( rst_p ) begin h_cnt <= 0; end else begin case( h_nx_state ) S_H_SYNC : begin if( h_pre_state == S_H_FRONT_PORCH ) //&& h_cnt == H_FRONT_PORCH -1 h_cnt <= 0; else h_cnt <= h_cnt + 1‘b1; end S_H_BACK_PORCH : begin if( h_pre_state == S_H_SYNC )//&& h_cnt == H_SYNC -1) h_cnt <= 0; else h_cnt <= h_cnt + 1‘b1; end S_H_ACTIVE : begin if( h_pre_state == S_H_BACK_PORCH)// && h_cnt == H_BACK_PORCH -1) h_cnt <= 0; else h_cnt <= h_cnt + 1‘b1; end S_H_FRONT_PORCH : begin if( h_pre_state == S_H_ACTIVE )//&& h_cnt == col -1) h_cnt <= 0; else h_cnt <= h_cnt + 1‘b1; end default:; endcase end end always @( posedge clk or posedge rst_p ) begin if( rst_p) v_cnt <= 0; else begin if( h_nx_state == S_H_FRONT_PORCH && h_pre_state == S_H_ACTIVE ) begin case( v_nx_state ) S_V_SYNC : begin if( v_pre_state == S_V_FRONT_PORCH ) v_cnt <= 0; else v_cnt <= v_cnt + 1‘b1; end S_V_BACK_PORCH : begin if( v_pre_state == S_V_SYNC ) v_cnt <= 0; else v_cnt <= v_cnt + 1‘b1; end S_V_ACTIVE : begin if( v_pre_state == S_V_BACK_PORCH ) v_cnt <= 0; else v_cnt <= v_cnt + 1‘b1; end S_V_FRONT_PORCH : begin if( v_pre_state == S_V_ACTIVE ) v_cnt <= 0; else v_cnt <= v_cnt + 1‘b1; end default:; endcase end end end /*********************************************************************** h_sync v_sync de ***********************************************************************/ always @( posedge clk ) begin if( h_nx_state == S_H_SYNC ) h_sync_r <= 1‘b1; else h_sync_r <= 1‘b0; end always @( posedge clk ) begin if( v_nx_state == S_V_SYNC ) v_sync_r <= 1‘b1; else v_sync_r <= 1‘b0; end always @( posedge clk ) begin if( h_nx_state == S_H_ACTIVE && v_nx_state == S_V_ACTIVE ) de_r <= 1‘b1; else de_r <= 1‘b0; end /*********************************************************************** ***********************************************************************/ always @( posedge clk ) begin if( h_nx_state == S_H_ACTIVE && v_nx_state == S_V_ACTIVE ) sync_code <= 16‘d0; else if(( h_nx_state == S_H_BACK_PORCH) && ( v_nx_state == S_V_SYNC || v_nx_state == S_V_BACK_PORCH || v_nx_state == S_V_FRONT_PORCH)) case( h_cnt ) H_BACK_PORCH -2 : sync_code <= 16‘habab;//16‘hab00;// H_BACK_PORCH -3 : sync_code <= 16‘h0000;//16‘h00ff;// H_BACK_PORCH -4 : sync_code <= 16‘h0000;//16‘h8010;// H_BACK_PORCH -5 : sync_code <= 16‘hffff;//16‘h8010;// default:sync_code <= 16‘h1080; endcase else if(( h_nx_state == S_H_FRONT_PORCH) && ( v_nx_state == S_V_SYNC || v_nx_state == S_V_BACK_PORCH || v_nx_state == S_V_FRONT_PORCH)) if( h_pre_state == S_H_ACTIVE) sync_code <= 16‘hffff;//16‘h00ff;// else begin case(h_cnt ) 0 : sync_code <= 16‘h0000;//16‘hb600;// 1 : sync_code <= 16‘h0000;//16‘h8010;// 2 : sync_code <= 16‘hb6b6;//16‘h8010;// default:sync_code <= 16‘h1080; endcase end else if(( h_nx_state == S_H_BACK_PORCH)) begin // && ( v_nx_state == S_V_ACTIVE) case(h_cnt ) H_BACK_PORCH -2 : sync_code <= 16‘h8080;//16‘h8000;// H_BACK_PORCH -3 : sync_code <= 16‘h0000;//16‘h00ff;// H_BACK_PORCH -4 : sync_code <= 16‘h0000;//16‘h8010;// H_BACK_PORCH -5 : sync_code <= 16‘hffff;//16‘h8010;// default:sync_code <= 16‘h1080; endcase end else if(( h_nx_state == S_H_FRONT_PORCH)) begin// && ( v_nx_state == S_V_ACTIVE) if( h_pre_state == S_H_ACTIVE) sync_code <= 16‘hffff;//16‘h00ff;// else begin case(h_cnt ) 0 : sync_code <= 16‘h0000;//16‘h9d00;// 1 : sync_code <= 16‘h0000;//16‘h8010;// 2 : sync_code <= 16‘h9d9d;//16‘h8010;// default:sync_code <= 16‘h1080; endcase end end else begin sync_code <= 16‘h1080; end end /*********************************************************************** sync ***********************************************************************/ always @( posedge clk ) begin sync_code_r <= sync_code; sync_code_r1<= sync_code_r; de_r1 <= de_r; de_r2 <= de_r1; h_sync_r1 <= h_sync_r; h_sync_r2 <= h_sync_r1; v_sync_r1 <= v_sync_r; v_sync_r2 <= v_sync_r1; end always @( posedge clk ) begin odata <= sync_code_r1 + fifo_rd_data_r; h_sync <= h_sync_r2; v_sync <= v_sync_r2; de <= de_r2; end endmodule
以上是关于BT1120时序，可以用于自测度的主要内容，如果未能解决你的问题，请参考以下文章
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