uvm transaction modeling
Posted 专注低功耗设计(2016)
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1.what is transaction?
network transactions
tcp/ip
wifi
3g/4g
bus transactions
amba-ahb/apb/axi
pci/pci-e
sata
usb
sd
instructions
x86
arm
2.uvm transaction flow
3.uvm modeling transaction
3.1 derived from uvm_sequence_item base class
built-in support for stimulus creation,printing,comparing,etc.
3.2 properties should be public by default
must be visible to contraints in other classes
3.3 properties should be rand by default
can be turned off with rand_mode
class transaction extends uvm_sequence_item;
rand bit [31:0] sa,sb;
rand bit [15:0] len;
rand bit [7:0] payload[$];
rand bit [31:0] fcs;
function new(string name="transaction");
super.new(name);
this.fcs.rand_mode(0);
endfunction
endclass:transaction
4.must obey contraints / should obey contraints
5.constraints considerations
total solution space
illegal solution space
valid solution space
test constraints
derived test constraints
6.uvm_sequence_item class tree
uvm_object: uvm_sequence_item
get_name() set_item_context()
get_full_name() set_transaction_id()
get_type() get_transaction_id()
clone() set_sequence_id()
copy() get_sequence_id()
print() set_id_info()
sprint() set_sequencer()
copy() get_sequencer()
compare() set_parent_sequence()
pack() get_parent_sequence()
unpack()
record()
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