基于FPGA的VGA显示设计
Posted yllinux
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参照 CrazyBingo 的 基于FPGA的VGA可移植模块终极设计代码 的工程代码风格，模块化处理了上一篇的代码，并增加了一点其它图形。
顶层模块：
1 /**************************************************** 2 * Module Name : VGA_color_all.v 3 * Author : yllinux 博客：http://www.cnblogs.com/yllinux/ 4 * Target Device : Cyclone IV E ( EP4CE6F17C8 ) 5 * Tool versions : Quartus II 12.1 6 * Create Date : 2017-7-29 7 * Revision : v1.0 8 * Description : 彩条显示模块化，并增加几种显示模式 9 *****************************************************/ 10 11 module VGA_color_all 12 ( 13 input clk, 14 input rst_n, 15 16 output hs, 17 output vs, 18 output [15:0] rgb 19 ); 20 21 /***************************************************** 22 分辨率选择，取消注释的有效 23 ******************************************************/ 24 //`define resolution_1280_1024_60FPS_108MHz 25 //`define resolution_1024_768_60FPS_65MHz 26 `define resolution_1920_1080_60FPS_148MHz 27 //`define resolution_ 28 //`define resolution_ 29 //`define resolution_800_600_72FPS_50MHz 30 //`define resolution_640_480_60FPS_25MHz 31 32 /**************************************************** 33 参数配置，其中的 DELAY 项可调 [0, 31] 34 ****************************************************/ 35 `ifdef resolution_1280_1024_60FPS_108MHz 36 parameter 37 DELAY = 5\'d3, //模式切换延时 38 DUTY_CYCLE = 50, //PLL占空比 39 DIVIDE_DATA = 25, //PLL除 40 MULTIPLY_DATA = 54, //PLL乘 41 PIXEL_FREQUENCY = 28\'d108_000000, //像素时钟，1秒 42 H_DISP = 12\'d1280, //行显示 Hor Addr Time 43 H_FRONT = 12\'d48, //行同步前 H Front Porch 44 H_SYNC = 12\'d112, //行同步 Hor Sync Time 45 H_BACK = 12\'d248, //行同步后 H Back Porch 46 H_TOTAL = 12\'d1688, //行总计 Hor Total Time 47 V_DISP = 12\'d1024, //场 Ver Addr Time 48 V_FRONT = 12\'d1, // V Front Porch 49 V_SYNC = 12\'d3, // Ver Sync Time 50 V_BACK = 12\'d38, // V Back Porch 51 V_TOTAL = 12\'d1066; // Ver Total Time 52 `endif 53 54 `ifdef resolution_800_600_72FPS_50MHz 55 parameter 56 DELAY = 5\'d3, 57 DUTY_CYCLE = 50, 58 DIVIDE_DATA = 1, 59 MULTIPLY_DATA = 1, 60 PIXEL_FREQUENCY = 28\'d50_000000, 61 H_DISP = 12\'d800, 62 H_FRONT = 12\'d56, 63 H_SYNC = 12\'d120, 64 H_BACK = 12\'d64, 65 H_TOTAL = 12\'d1040, 66 V_DISP = 12\'d600, 67 V_FRONT = 12\'d37, 68 V_SYNC = 12\'d6, 69 V_BACK = 12\'d23, 70 V_TOTAL = 12\'d666; 71 `endif 72 73 `ifdef resolution_640_480_60FPS_25MHz 74 parameter 75 DELAY = 5\'d3, 76 DUTY_CYCLE = 50， 77 DIVIDE_DATA = 2， 78 MULTIPLY_DATA = 1， 79 PIXEL_FREQUENCY = 28\'d25_000000, 80 H_DISP = 12\'d640, 81 H_FRONT = 12\'d16, 82 H_SYNC = 12\'d96, 83 H_BACK = 12\'d48, 84 H_TOTAL = 12\'d800, 85 V_DISP = 12\'d480, 86 V_FRONT = 12\'d10, 87 V_SYNC = 12\'d2, 88 V_BACK = 12\'d33, 89 V_TOTAL = 12\'d525; 90 `endif 91 92 `ifdef resolution_1024_768_60FPS_65MHz 93 parameter 94 DELAY = 5\'d3, 95 DUTY_CYCLE = 50, 96 DIVIDE_DATA = 10, 97 MULTIPLY_DATA = 13, 98 PIXEL_FREQUENCY = 28\'d65_000000, 99 H_DISP = 12\'d1024, 100 H_FRONT = 12\'d24, 101 H_SYNC = 12\'d136, 102 H_BACK = 12\'d160, 103 H_TOTAL = 12\'d1344, 104 V_DISP = 12\'d768, 105 V_FRONT = 12\'d3, 106 V_SYNC = 12\'d6, 107 V_BACK = 12\'d29, 108 V_TOTAL = 12\'d806; 109 `endif 110 111 `ifdef resolution_1920_1080_60FPS_148MHz 112 parameter 113 DELAY = 5\'d3, 114 DUTY_CYCLE = 50, 115 DIVIDE_DATA = 100, 116 MULTIPLY_DATA = 297, 117 PIXEL_FREQUENCY = 28\'d1485_00000, 118 H_DISP = 12\'d1920, 119 H_FRONT = 12\'d88, 120 H_SYNC = 12\'d44, 121 H_BACK = 12\'d148, 122 H_TOTAL = 12\'d2200, 123 V_DISP = 12\'d1080, 124 V_FRONT = 12\'d4, 125 V_SYNC = 12\'d5, 126 V_BACK = 12\'d36, 127 V_TOTAL = 12\'d1125; 128 `endif 129 130 `ifdef resolution 131 parameter 132 DELAY = 5\'d3, 133 DUTY_CYCLE = 134 DIVIDE_DATA = 135 MULTIPLY_DATA = 136 PIXEL_FREQUENCY = 28\'d 137 H_DISP = 12\'d 138 H_FRONT = 12\'d 139 H_SYNC = 12\'d 140 H_BACK = 12\'d 141 H_TOTAL = 12\'d 142 V_DISP = 12\'d 143 V_FRONT = 12\'d 144 V_SYNC = 12\'d 145 V_BACK = 12\'d 146 V_TOTAL = 12\'d 147 `endif 148 149 /************************************************ 150 clk_pll instantiation （PLL核实例化） 151 *************************************************/ 152 wire clk_vga; 153 clk_pll //模块名 154 #( 155 .DUTY_CYCLE ( DUTY_CYCLE ), 156 .DIVIDE_DATA ( DIVIDE_DATA ), 157 .MULTIPLY_DATA ( MULTIPLY_DATA ) 158 ) 159 clk_pll_inst //实例化名 160 ( 161 .inclk0 ( clk ), 162 .c0 ( clk_vga ) 163 ); 164 165 /************************************************ 166 display_vga instantiation （显示模块实例化） 167 *************************************************/ 168 //wire [11:0] xpos_vga_driver; 169 //wire [11:0] ypos_vga_driver; 170 //wire [15:0] data_vga_driver; 171 wire [11:0] xpos_vga; //例化括号里代表连线的名称，上面注释的三条是错的 172 wire [11:0] ypos_vga; 173 wire [15:0] data_vga; 174 display_vga //模块名 175 #( //参数传递 176 .H_DISP ( H_DISP ), 177 .V_DISP ( V_DISP ), 178 .PIXEL_FREQUENCY ( PIXEL_FREQUENCY ), 179 .DELAY ( DELAY ) 180 ) 181 display_vga_inst //实例化名 182 ( 183 .clk_vga_display ( clk_vga ), 184 .rst_n_display ( rst_n ), 185 .xpos_vga_display ( xpos_vga ), 186 .ypos_vga_display ( ypos_vga ), 187 188 .data_vga_display ( data_vga ) 189 ); 190 191 /************************************************ 192 driver_vga instantiation （驱动模块实例化） 193 *************************************************/ 194 driver_vga 195 #( 196 .H_DISP ( H_DISP ), 197 .H_FRONT ( H_FRONT ), 198 .H_SYNC ( H_SYNC ), 199 .H_BACK ( H_BACK ), 200 .H_TOTAL ( H_TOTAL ), 201 .V_DISP ( V_DISP ), 202 .V_FRONT ( V_FRONT ), 203 .V_SYNC ( V_SYNC ), 204 .V_BACK ( V_BACK ), 205 .V_TOTAL ( V_TOTAL ) 206 ) 207 driver_vga_inst 208 ( 209 .clk_vga_driver ( clk_vga ), 210 .rst_n_driver ( rst_n ), 211 .data_vga_driver ( data_vga ), 212 213 .rgb_vga_driver ( rgb ), 214 .hs_vga_driver ( hs ), 215 .vs_vga_driver ( vs ), 216 .xpos_vga_driver ( xpos_vga ), 217 .ypos_vga_driver ( ypos_vga ) 218 ); 219 220 endmodule
驱动模块：
1 module driver_vga 2 #( 3 /*********************************************** 4 1280 x 1024 @ 60 Hz 5 ***********************************************/ 6 parameter 7 H_DISP = 12\'d1280, //行显示 Hor Addr Time 8 H_FRONT = 12\'d48, //行同步前 H Front Porch 9 H_SYNC = 12\'d112, //行同步 Hor Sync Time 10 H_BACK = 12\'d248, //行同步后 H Back Porch 11 H_TOTAL = 12\'d1688, //行总计 Hor Total Time 12 13 V_DISP = 12\'d1024, //场 Ver Addr Time 14 V_FRONT = 12\'d1, // V Front Porch 15 V_SYNC = 12\'d3, // Ver Sync Time 16 V_BACK = 12\'d38, // V Back Porch 17 V_TOTAL = 12\'d1066 // Ver Total Time 18 ) 19 ( 20 input clk_vga_driver, //VGA像素时钟 21 input rst_n_driver, //异步复位信号，低电平有效 22 input [15:0] data_vga_driver, //RGB565格式 23 24 output [15:0] rgb_vga_driver, //接收要显示的色彩 25 output reg hs_vga_driver, //VGA管脚 行同步 26 output reg vs_vga_driver, //VGA管脚 场同步 27 output [11:0] xpos_vga_driver, //像素横坐标位置 28 output [11:0] ypos_vga_driver //像素纵坐标位置 29 ); 30 31 /***************************************************** 32 驱动核心，行场同步信号发生器与同步 33 *****************************************************/ 34 reg [11:0] hcnt; //定义行计数器 35 always @ (posedge clk_vga_driver or negedge rst_n_driver) 36 begin 37 if (!rst_n_driver) 38 hcnt <= 12\'d0; 39 else 40 begin 41 if (hcnt <= H_TOTAL - 12\'d1) //行计数取值区间【0, H_TOTAL - 1】 42 hcnt <= hcnt + 12\'d1; 43 else 44 hcnt <= 12\'d0; 45 end 46 end 47 always @ (posedge clk_vga_driver or negedge rst_n_driver) 48 begin 49 if (!rst_n_driver) 50 hs_vga_driver <= 1\'b0; 51 else 52 begin 53 // 像素点区间【H_DISP + H_FRONT, H_DISP +H_FRONT + H_SYNC -1】 54 if (hcnt >= H_DISP + H_FRONT - 12\'d1 && hcnt < H_DISP +H_FRONT + H_SYNC - 12\'d1) 55 hs_vga_driver <= 1\'b1; 56 else 57 hs_vga_driver <= 1\'b0; 58 end 59 end 60 61 reg [11:0] vcnt; 62 always @ (posedge clk_vga_driver or negedge rst_n_driver) 63 begin 64 if (!rst_n_driver) 65 vcnt <= 12\'d0; 66 else 67 begin 68 if (hcnt == H_DISP - 12\'d1) 69 begin 70 if (vcnt < V_TOTAL - 12\'d1) 71 vcnt <= vcnt + 12\'d1; 72 else 73 vcnt <= 12\'d0; 74 end 75 else 76 vcnt <= vcnt; 77 end 78 end 79 always @ (posedge clk_vga_driver or negedge rst_n_driver) 80 begin 81 if (!rst_n_driver) 82 vs_vga_driver <= 1\'b0; 83 else 84 begin 85 if (vcnt >= V_DISP + V_FRONT - 12\'d1 && vcnt < V_DISP + V_FRONT + V_SYNC - 12\'d1) 86 vs_vga_driver <= 1\'b1; 87 else 88 vs_vga_driver <= 1\'b0; 89 end 90 end 91 92 /************************************************************ 93 输出横竖坐标和有效区域数据 94 ************************************************************/ 95 assign xpos_vga_driver = (hcnt < H_DISP) ? hcnt : 12\'d0; //把显示期的行计数值赋给横坐标变量 96 assign ypos_vga_driver = (vcnt < V_DISP) ? vcnt : 12\'d0; //把显示期的场计数值赋给纵坐标变量 97 assign rgb_vga_driver = (hcnt < H_DISP && vcnt < H_DISP) ? data_vga_driver : 16\'d0; //显示期进行图像输出 98 99 endmodule
显示模块：
1 module display_vga 2 #( 3 /*********************************************** 4 1280 x 1024 @ 60 Hz 5 ***********************************************/ 6 parameter 7 H_DISP = 12\'d1280, 8 V_DISP = 12\'d1024, 9 PIXEL_FREQUENCY = 28\'d108_000000, 10 DELAY = 5\'d3 11 ) 12 ( 13 input clk_vga_display, 14 input rst_n_display, 15 input [11:0] xpos_vga_display, //输入横坐标 16 input [11:0] ypos_vga_display, //输入纵坐标 17 18 output reg [15:0] data_vga_display //输出产生的图像数据 19 ); 20 21 /**************************************************************** 22 定义本地参数颜色，RGB565 23 ****************************************************************/ 24 localparam 25 RED = 16\'hF800, //11111_000000_00000 红 26 GREEN = 16\'h07E0, //00000_111111_00000 绿 27 BLUE = 16\'h001F, //00000_000000_11111 蓝 28 WHITE = 16\'hFFFF, //11111_111111_11111 白 29 BLACK = 16\'h0000, //00000_000000_00000 黑 30 YELLOW = 16\'hFFE0, //11111_111111_00000 黄 31 MAGENTA= 16\'hF81F, //11111_000000_11111 紫（品红、洋红） 32 CYAN = 16\'h07FF; //00000_111111_11111 青（蓝绿） 33 34 /**************************************************************** Verilog基于FPGA的打地鼠小游戏设计（VGA显示附代码演示视频）