What makes an inferred latch? how To avoid creating inferred latches? when do you know you need lat
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What makes an inferred latch?
For combinatorial logic, the output of the circuit is a function of input only and should not contain any memory or internal state (latch).
In Verilog, a variable will keep its previous value if it is not assigned a value in an always block. A latch must be created to store this present value.
An incomplete if-else statement will generate latches. An if-else statement is considered "incomplete" if the output state is not defined for all possible input conditions. The same goes for an incomplete case statement, or a case statement that does not have a default: item.
Why are inferred latches bad?
Inferred latches can serve as a ‘warning sign‘ that the logic design might not be implemented as intended. A crucial if-else or case statement might be missing from the design.
Latches can lead to timing issues and race conditions. They may lead to combinatorial feedback - routing of the output back to the input - which can be unpredictable.
To avoid creating inferred latches:
Include all the branches of an if or case statement
Assign a value to every output signal in every branch
Use default assignments at the start of the procedure, so every signal will be assigned.
Some parts paraphrased from "FPGA Prototyping by Verilog Examples" by P. Chu
when do you know you need latches?
Which, as you implied, is a subjective question. Expect more opinion than fact as answers. That being said, here is my opinion:
I, like you, often find better ways to use flip-flops thus avoiding latches. The resulting logic is often more elegant and robust. But there are times where I don‘t have enough control over the logic to avoid latches. For example, I might be interfacing to a processor bus that requires latches to meet the desired specifications. Since I can‘t redesign the CPU or the bus, I‘m stuck with the latch.
In the past 13+ years, that is the only time I have needed latches.
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