I.MX6 AR8031 寄存器操作

Posted 2020-09-10 zengjf

/***************************************************************************
 *                         I.MX6 AR8031 寄存器操作
 * 说明：
 *     解读一下AR8031这颗PHY的寄存器要如何操作，了解PHY的MDIO是如何操作的。
 *
 *                                    2017-4-12 深圳 龙华民治樟坑村 曾剑锋
 **************************************************************************/

一、. 参考文档：
    DataShet：AR8031 Integrated 10/100/1000 Mbps Ethernet Transceiver

二、参考数据手册：4.1 Register Summary：
    Three types of registers are present on AR8031: 
    1. IEEE defined 32 MII registers, referred to as "registers" in this document
    – MII registers are accessed directly through the management frame.
    2. Atheros defined debug registers, referred to as "debug registers" in this document
    – Write debug offset address to 0x1D
    – Read/write the data from/to 0x1E
    3. IEEE defined MDIO Manageable Device (MMD) register, referred to as "MMD registers" in this document
    – MMD register access: refer to "MDIO Interface Register".
    Example: Writing 0x8000 to register 0 of MMD3.
        1. Write 0x3 to register 0xD: 0xD = 0x0003; (function = address; set the device address)
        2. Write 0x0 to register 0xE: 0xE = 0x0; (set the register offset address)
        3. Write 0x4003 to register 0xD:0xD=0x4003; (function = data; keep the device address)
        4. Read register 0xE:0xE == (data from register 0x0 of MMD3)
        5. Write 0x8000 to register 0xE: 0xE = 0x8000 (write 0x8000 to register 0x0 of MMD3)
        NOTE: Read operation follows the process 1 to 4.

三、Register Summary翻译
    AR8031有三种类型的寄存器：
    1. IEEE定义的32个MII寄存器，参考本文档的registers部分
    – MII寄存器可以寄存器直接访问；
    2. Atheros定义的debug寄存器，参考本文档的debug registers部分
    – 在MII寄存器的0x1D中写入debug寄存器的偏移地址
    – 在MII寄存器的0x1E中读/写debug寄存器的值
    3. IEEE defined MDIO Manageable Device (MMD) register, referred to as "MMD registers" in this document
    3. IEEE定义的MDIO设备管理寄存器，参考本文档的MMD registers部分
    – MMD寄存器访问，参考MDIO Interface Register
    示例：往MMD3，偏移地址0寄存器中写入0x8000：
        1. 将0x3写入0xD寄存器中；
        2. 将0x0写入0xE寄存器中；
        3. 将0x4003写入0xD寄存器中；
        4. 读取0xE寄存器的值；
        5. 将0x8000写入0xE寄存器中；
        注意：读操作过程只需要关注1到4中的步骤即可。

四、操作解析：
    1. MII Registers
        ...
        0x0D "MMD Access Control Register" on page 67
        0x0E "MMD Access Address Data Register" on page 67
        ...
        0x1D "Debug Port (Address offset set)" on page 80
        0x1E "Debug Port2 (R/W port)" on page 80
        ...
    2. 如上可知，Atheros定义的debug寄存器和MMD寄存器都是通过32个MII寄存器中的寄存器间接访问的。
    3. MMD Access Control Register（0x0D）(page 67, 4.2.19 MMD Access Control Register)：
        1. 控制对应的数据寄存器是地址还是数据；
            1. 控制如果是地址，连续读取数据，地址会不会自动增加；
            2. 控制如果是地址，连续写入数据，地址会不会自动增加；
        2. MDIO 接口寄存器分成两组(page 87, 4.4 MDIO Interface Register)：
            1. MMD3 – MDIO Manageable Device Address 3 for PCS
            2. MMD7 – MDIO Manageable Device Address 7 for Auto-Negotiation # 自动协商
    3. 示例解析：
        1. 将0x3写入0xD表示：选用MMD3接口寄存器，并且数据寄存器中存放的是地址；
        2. 将0x0写入0xE表示：往数据寄存器中写入地址数据0x0；
        3. 将0x4003写入0xD表示：选用MMD3接口寄存器，并且数据寄存器中存放的是数据，读写不自增；
        4. 读0xE进行读写：读取、写入数据寄存器；

五、i.MX6 ar8031_phy_fixup hacking
    static int ar8031_phy_fixup(struct phy_device *dev)
    {
        u16 val;

        /* Set RGMII IO voltage to 1.8V */
        // 这个电压寄存器找不到
        phy_write(dev, 0x1d, 0x1f);
        phy_write(dev, 0x1e, 0x8);

        /* disable phy AR8031 SmartEEE function. */
        phy_write(dev, 0xd, 0x3);
        phy_write(dev, 0xe, 0x805d);
        phy_write(dev, 0xd, 0x4003);
        val = phy_read(dev, 0xe);
        val &= ~(0x1 << 8);
        phy_write(dev, 0xe, val);

        /* To enable AR8031 output a 125MHz clk from CLK_25M */
        // page 112, Chapter: 4.4.77 CLK_25M Clock Select
        phy_write(dev, 0xd, 0x7);
        phy_write(dev, 0xe, 0x8016);
        phy_write(dev, 0xd, 0x4007);

        val = phy_read(dev, 0xe);
        val &= 0xffe3;      // mask 0b1111 1111 1110 0011
        val |= 0x18;        // 110 = 125 MHz from local PLL source
        phy_write(dev, 0xe, val);

        /* introduce tx clock delay */
        // page 83, Chapter: 4.3.2 SerDes Test and System Mode Control
        phy_write(dev, 0x1d, 0x5);
        val = phy_read(dev, 0x1e);
        val |= 0x0100;      // 1 = rgmii tx clock delay enable
        phy_write(dev, 0x1e, val);

        return 0;
    }