X-007 FriendlyARM tiny4412 u-boot移植之内存初始化

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开发环境:win7 64 + VMware12 + Ubuntu14.04 64

工具链:linaro提供的gcc-linaro-6.1.1-2016.08-x86_64_arm-linux-gnueabi

要移植的u-boot版本:u-boot-2016-11

Tiny4412开发板硬件版本为

    底板:  Tiny4412/Super4412SDK 1506

       核心板:Tiny4412 - 1412

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> 

 

在上一节中我们把tiny4412开发板上的COM0串口用起来,可以通过COM0串口输出一些调试信息。接下来要做的是初始化tiny4412开发板上的DDR3内存。

 

1Tiny4412开发板上的DDR3内存

   原理图:Tiny4412-1412-Schematic.pdf

clip_image002

从原理图上可以看出,使用2K4B4G1646B-HCK内存芯片并联组成了数据位为32bit 1G大小的内存。内存芯片接在exynos4412芯片的DMC0上,使用了一个chip(chip0),内存地址空间为0x40000000-0x80000000

 

2Exynos4412芯片DMC初始化步骤

具体信息在 《Exynos 4412 SCP_Users Manual_Ver.0.10.00_Preliminary.pdf》第18Dynamic Memory Controller

clip_image004

clip_image006

 

3Tiny4412 DDR3初始化代码

diff --git a/arch/arm/mach-exynos/dmc_init_exynos4412.c b/arch/arm/mach-exynos/dmc_init_exynos4412.c

new file mode 100644

index 0000000..27f72cd

--- /dev/null

+++ b/arch/arm/mach-exynos/dmc_init_exynos4412.c

@@ -0,0 +1,254 @@

+/*

+ * Memory setup for board based on EXYNOS4412

+ *

+ *                 2016

+ * Modified by AP0904225 <ap0904225@qq.com>

+ *

+ * Copyright (C) 2013 Samsung Electronics

+ * Rajeshwari Shinde <rajeshwari.s@samsung.com>

+ *

+ * See file CREDITS for list of people who contributed to this

+ * project.

+ *

+ * This program is free software; you can redistribute it and/or

+ * modify it under the terms of the GNU General Public License as

+ * published by the Free Software Foundation; either version 2 of

+ * the License, or (at your option) any later version.

+ *

+ * This program is distributed in the hope that it will be useful,

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+ * GNU General Public License for more details.

+ *

+ * You should have received a copy of the GNU General Public License

+ * along with this program; if not, write to the Free Software

+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,

+ * MA 02111-1307 USA

+ */

+

+#include <config.h>

+#include <asm/arch/dmc.h>

+#include "common_setup.h"

+#include "exynos4412_setup.h"

+

+#ifdef TINY4412

+struct mem_timings mem = {

+   .direct_cmd_msr = {

+       DIRECT_CMD1, DIRECT_CMD2, DIRECT_CMD3, DIRECT_CMD4

+   },

+   .timingref   = 0x000000BB,

+   .timingrow   = 0x6946654f,

+   .timingdata  = 0x46460506,

+   .timingpower = 0x5200183c,

+   .zqcontrol   = 0xE3854C03,

+   .control0    = 0x71101008,

+   .control1    = 0xe0000086,

+   .control2    = 0x00000000,

+   .concontrol  = 0x0FFF301A,

+   .prechconfig = 0xff000000,

+   .memcontrol  = 0x00302640,      /* Tiny4412-1412 core board only use chip0 */

+   .memconfig0  = 0x40C01333,      /* ROW is 15bit */

+   .memconfig1  = 0x80C01333,      /* DMC0 address up to 0x7FFFFFFF */

+   .dll_resync  = FORCE_DLL_RESYNC,

+   .dll_on      = DLL_CONTROL_ON,

+

+};

+#else

+struct mem_timings mem = {

+   .direct_cmd_msr = {

+       DIRECT_CMD1, DIRECT_CMD2, DIRECT_CMD3, DIRECT_CMD4

+   },

+   .timingref = TIMINGREF_VAL,

+   .timingrow = TIMINGROW_VAL,

+   .timingdata = TIMINGDATA_VAL,

+   .timingpower = TIMINGPOWER_VAL,

+   .zqcontrol = ZQ_CONTROL_VAL,

+   .control0 = CONTROL0_VAL,

+   .control1 = CONTROL1_VAL,

+   .control2 = CONTROL2_VAL,

+   .concontrol = CONCONTROL_VAL,

+   .prechconfig = PRECHCONFIG,

+   .memcontrol = MEMCONTROL_VAL,

+   .memconfig0 = MEMCONFIG0_VAL,

+   .memconfig1 = MEMCONFIG1_VAL,

+   .dll_resync = FORCE_DLL_RESYNC,

+   .dll_on = DLL_CONTROL_ON,

+};

+#endif

+

+static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc)

+{

+   if (ctrl_no) {

+       writel((mem.control1 | (1 << mem.dll_resync)),

+              &dmc->phycontrol1);

+       writel((mem.control1 | (0 << mem.dll_resync)),

+              &dmc->phycontrol1);

+   } else {

+       writel((mem.control0 | (0 << mem.dll_on)),

+              &dmc->phycontrol0);

+       writel((mem.control0 | (1 << mem.dll_on)),

+              &dmc->phycontrol0);

+   }

+}

+

+static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip)

+{

+   int i;

+   unsigned long mask = 0;

+

+   if (chip)

+       mask = DIRECT_CMD_CHIP1_SHIFT;

+

+   for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {

+       writel(mem.direct_cmd_msr[i] | mask,

+              &dmc->directcmd);

+   }

+}

+

+static void dmc_init(struct exynos4_dmc *dmc)

+{

+   /*

+    * DLL Parameter Setting:

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