verilog状态机

Posted 2020-06-14

如下是官网quartus的帮助文档中的说明。

A state machine is a sequential circuit that advances through a number of states. By default, the Quartus II software automatically infers state machines in your Verilog HDL code by finding variables whose functionality can be replaced by a state machine without changing the simulated behavior of your design. If you wish to disable automatic inference of state machines in Verilog HDL, set the value of the logic option to Off.

The Quartus II software infers state machines for all registered, unsigned vector variables that satisfy the following conditions:

• The variable is not declared as a module output

• The values assigned to the variable are constant literals, parameters, enums (SystemVerilog), or other state variables.

• The variable has more than two states, in other words, it was assigned at least two distinct constant values.

• The variable is not indexed in an expression or referenced as an operand in an arithmetic expression. The latter condition prohibits state transition logic based on arithmetic relationship among the states, for example, next_state <= state + 1.

• The variable has at most one asynchronous reset condition.

If a variable satisfies these conditions, the Quartus II software recognizes the variable as a state machine and report it in the compilation report. Variables that do not meet these conditions are extracted as regular logic and not reported as a state machines.

Note:Use parameters or enumeration literals (SystemVerilog) to represent the states of your state machine. The Quartus II software uses the names of the parameters or enumeration literals when referring to the states. If you use constant literals to represent states, the Quartus II software uses those constant literals as the names of the states, which often makes for a less intuitive state machine.

The following Verilog HDL example implements a 3-state state machine.

module state_machine (clk, in, reset, out); input   clk, in, reset; output  [1:0]out; reg     [1:0]out; reg     [1:0]state; parameter S0 = 0, S1 = 1, S2 = 2; always @ (state) begin case (state) S0: out = 2‘b01; S1: out = 2‘b10; S2: out = 2‘b11; default: out = 2‘b00; endcase end always @ (posedge clk or posedge reset) begin if (reset) state <= S0; else case (state) S0: state <= S1; S1: if (in) state <= S2; else state <= S1; S2: if (in) state <= S0; else state <= S1; endcase end endmodule

This state machine includes a combinational always construct to model the output logic and a sequential (edge-triggered) always construct to model that state variable. The state variable reg [1:0]state stores the current state of the state machine. The parameters S0, S1, and S2represent the states of the state machine.

At power-up, the state machine initializes to the reset state S0. If there were no explicit reset state, the state machine would initialize to the state with value 0, which for this example is also S0. If there were no state with the value 0, the Quartus II software would choose an arbitrary state to be the reset state.

For more information, see the following sections of the IEEE Std 1394-2001 IEEE Hardware Description Language Based on the Verilog Hardware Description Languagemanual:

• Section 9.2: Procedural Assignments

• Section 9.4: Conditional Statements

• Section 9.5: Case Statements

• Section 9.7.2: Event Control

• Section 9.9.2: Always Constructs