帮我详细解读一下这个分频模块啊

Posted 2023-02-27

分频器:将50MHZ的系统时钟转变为1MHZ，再将1MHZ时钟信号进一步分频，变为500KHZ
部分程序如下
process(reset,clk) --clk=50MHz
begin
if(reset='0')then
cnt_distance<="00000";
elsif(clk'event and clk='1')then
if(cnt_distance="11000")then
cnt_distance<="00000";
else
cnt_distance<=cnt_distance+1;
end if;
end if;
end process;
clk_d<='1' when cnt_distance="11000" else
'0';

参考技术A process(reset,clk) --clk=50MHz //sensitive signals
begin
if(reset='0')then
cnt_distance<="00000"; //if reset is low, then let the cnt_distance=00000B
elsif(clk'event and clk='1')then //if reset is high and there is a posedge of clk
if(cnt_distance="11000")then //and the counter(cnt_distance) is counted to 11000B
cnt_distance<="00000"; //set the counter as 00000
else //otherwise the counter begin to count (that means let the counter plus 1)
cnt_distance<=cnt_distance+1;
end if;
end if;
end process;
clk_d<='1' when cnt_distance="11000" else
'0'; //every period the program wil detect the counter's value, if the value equals to 11000B , then the clk_d will become high, last for one period, and at the next period, the clk_d wil be set back to low (because when the counter's value is up to 11000B, it wil be set as 00000B)

P.S.
why the max value of the counter(cnt_distance) should be set as 11000B?
though 11000B=24D, actually this should be a 25-band counter.
so when a 50MHz clock input this moudle, it will be devide into a 25-period low and 25-period high clock.

by the way, the clk_d should NOT be the final divided clock output, just for a warning本回答被提问者采纳