如何在每个计数器更新（可变整数范围）发送一点？

Question

我用VHDL（简单）为我的I2S收发器编写了一个代码。我必须知道在每次计数器更新之后如何发送1,2,3（24位）I2S字的24位之一（带有简短陈述）。例如：

if cnt = 2 => load bit 1 of left channel
if cnt = 3 => load bit 2
if cnt = 25 => load bit 24 of left channel
if cnt = 26 => load bit 1 of right channel
if cnt = 48 => load bit 24 of right channel

如您所见，我的代码中的WS选择左或右通道。在我的测试平台中，我添加了测试字（2 x 24位字）。

它是并行数据输入和串行输出（PISO），所以它必须像移位寄存器。

我最近一直在研究VHDL，因为我是VHDL的新手，但我不知道该怎么做。

在这里你可以看到我的书面代码。也许这是一个愚蠢的问题，但我已经搜索了整个互联网。提前谢谢你回答我的问题。

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Simple_I2S_transceiver_V1 is
generic  (
    DATAWIDTH: integer := 24     
   );

port  
   (
    RST  : in std_logic;
    SCK  : in std_logic;             -- Serial Clock
    BCLK   : in std_logic;             -- Bit Clock
    WS   : inout std_logic;            -- Word Select or Left/Right channel select
    SD     : out std_logic;             -- Serial Data
    PDL  : in std_logic_vector(DATAWIDTH - 1 downto 0);   -- Parallel Data Left
    PDR  : in std_logic_vector(DATAWIDTH - 1 downto 0);   -- Parallel Data Right
    UPD  : inout std_logic;             -- Update data
    READY  : out std_logic;             -- check if data is ready to send (it depends on "VALID")
    VALID  : out std_logic             -- Check if data is valid (length) 
   );

end Simple_I2S_transceiver_V1;

architecture behavior of Simple_I2S_transceiver_V1 is
signal PDL_BUF : std_logic_vector(DATAWIDTH - 1 downto 0);
signal PDR_BUF : std_logic_vector(DATAWIDTH - 1 downto 0);
begin 

process(BCLK)

 -- Declaration of optional variables 
 variable bitcounter  : integer range 0 to 48;

 begin
  -------------------------------------------------
  -- RESET all     
  -------------------------------------------------

  if RST = '1' then
   WS  <= '0';
   SD  <= '0';
   READY <= '0';
   VALID <= '0';
   UPD   <= '0';
   PDL_BUF <= (OTHERS => '0');                                         -- Clear left channel buffer
   PDR_BUF <= (OTHERS => '0');                 -- Clear right channel buffer
      -------------------------------------------------
  -- Set WS / left/right-channel
      -------------------------------------------------

  elsif (BCLK'event and BCLK = '1') then
   PDL_BUF <= PDL;
   PDR_BUF <= PDR;

   bitcounter := bitcounter + 1;

   if bitcounter = 1 then
    UPD <= '1';
   else 
    UPD <= '0';

   if bitcounter >= 1 and bitcounter <= 24 then  
    WS <= '0';
   else
    WS <= '1';
    UPD <= '0'; 

   if WS = '0' then
    SD <= PDL(23);         <-- Parallel load -> it has to be serial load
   elsif WS = '1' then
    SD <= PDR(23);         <-- The same as PDL

   if bitcounter = 48 then
    bitcounter := 0;

   ----------------------------------------------
     -- transmitt data
   ---------------------------------------------- 
   -- add transmission 

     end if;
       end if;
      end if;
    end if;
   end if;
end process;

end behavior;