如何定位我的变量是多驱动的？
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我得到一个多驱动的错误。我不知道如何解决这个问题。我正试图为一个简单的计算器写一个代码，我认为这是一个在一个模块中使用组合和时钟设计的问题。我认为这是一个在一个模块中使用组合和时钟设计的问题。
当我删除输出逻辑时，执行成功；但当我添加输出逻辑时，我得到了多驱动错误。 Verilog显示，该代码在多个方面是多驱动的。
Verilog说regs ones,tens,hundreds,thous,and neg是多驱动的。
`timescale 1ns / 1ps
module project2(w,clock,reset,error,Z);
input [3:0] w;
output error;
input clock,reset;
wire [16:0] answer;
reg [3:0]thousands,hundreds,tens,ones,operand;
reg [3:0]thousandsB,hundredsB,tensB,onesB;
reg [1:0] Operator;
reg errordisp,neg,negB;
wire [15:0]A2,B2,Z1,Result;
reg [16:0] A,B;
output reg [19:0]Z;
reg [3:0] next,present;
parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010,
sign = 4'b1111, blk = 4'b1110, add = 4'b1010, sub = 4'b1011, mult = 4'b1100, div = 4'b1101, enter = 4'b1110;
// OUTPUT LOGIC
always @(w,present)
case( present)
S0: Z = blk,blk,blk,blk,4'b0;
S1: if (neg==1) Z = blk,blk,blk,sign,ones;
else Z = blk,blk,blk,blk,ones;
S2: if (neg==1) Z = blk,blk,sign,tens,ones;
else Z = blk,blk,blk,tens,ones;
S3: if (neg==1) Z = blk,sign,hundreds,tens,ones;
else Z = blk,blk,hundreds,tens,ones;
S4: if (neg==1) Z = sign,thousands,hundreds,tens,ones;
else Z = blk,thousands,hundreds,tens,ones;
S5:begin
if ((A[16] == 1'b0)&&(A[15:12] == 0)&&(A[11:8] == 0)&&(A[7:4] == 0)&&( A[3:0]!= 0))
Z = blk,blk,blk,blk,A[3:0];
else if ((A[16] == 1'b1)&&(A[15:12] == 0)&&(A[11:8] == 0)&&(A[7:4] == 0)&&( A[3:0]!= 0))
Z = blk,blk,blk,sign,A[3:0];
else if ((A[16] == 1'b0)&&(A[15:12] == 0)&&(A[11:8] == 0)&&(A[3:0] != 0))
Z = blk,blk,blk,A[7:4],A[3:0];
else if ((A[16] == 1'b1)&&(A[15:12] == 0)&&(A[11:8] == 0)&&(A[3:0] != 0))
Z = blk,blk,sign,A[7:4],A[3:0];
else if ((A[16] == 1'b0)&&(A[15:12] == 0)&&(A[11:8] != 0))
Z = blk,blk,A[11:8],A[7:4],A[3:0];
else if ((A[16] == 1'b1)&&(A[15:12] == 0)&&(A[11:8] != 0))
Z = blk,sign,A[11:8],A[7:4],A[3:0];
else if ((A[16] == 1'b1)&&(A[15:12] != 0))
Z = sign,A[15:12],A[11:8],A[7:4],A[3:0];
else if ((A[16] == 1'b0)&&(A[15:12] != 0))
Z = blk,A[15:12],A[11:8],A[7:4],A[3:0];
else if ((A[16] == 1'b1)&&(A[15:12] == 0)&&(A[11:8] == 0)&&(A[7:4] != 0)&&( A[3:0]== 0))
Z = blk,blk,sign,A[7:4],A[3:0];
else if ((A[16] == 1'b0)&&(A[15:12] == 0)&&(A[11:8] == 0)&&(A[7:4] != 0)&&( A[3:0]== 0))
Z = blk,blk,blk,A[7:4],A[3:0];
else if ((A[16] == 1'b0)&&(A[15:12] == 0)&&(A[11:8] == 0)&&(A[7:4] == 0)&&( A[3:0]== 0))
Z = blk,blk,blk,blk,4'b0;
else
Z = blk,blk,blk,blk,blk;
end
S6:begin
if(negB == 1'b0)
Z = blk,blk,blk,blk,onesB;
else if(negB == 1'b1)
Z = blk,blk,blk,sign,onesB;
else
Z = blk,blk,blk,blk,onesB;
end
//end
S7:begin
if((negB == 1'b1)&&( tensB != 0))
Z = blk,blk,sign,tensB,onesB;
else if ((negB == 1'b0)&&( tensB != 0))
Z = blk,blk,blk,tensB,onesB;
else
Z = blk,blk,blk,blk,onesB;
end
S8:begin
if(negB == 1'b1)
Z = blk,sign,hundredsB,tensB,onesB;
else
Z = blk,blk,hundredsB,tensB,onesB;
end
S9:begin
if(negB == 1'b1)
Z = sign,thousandsB,hundredsB,tensB,onesB;
else
Z = blk,thousandsB,hundredsB,tensB,onesB;
end
S10:begin
if ((A[16] == 1'b0)&&(A[15:12] == 0)&&(A[11:8] == 0)&&(A[7:4] == 0)&&( A[3:0]!= 0))
Z = blk,blk,blk,blk,A[3:0];
else if ((A[16] == 1'b1)&&(A[15:12] == 0)&&(A[11:8] == 0)&&(A[7:4] == 0)&&( A[3:0]!= 0))
Z = blk,blk,blk,sign,A[3:0];
else if ((A[16] == 1'b0)&&(A[15:12] == 0)&&(A[11:8] == 0)&&(A[3:0] != 0))
Z = blk,blk,blk,A[7:4],A[3:0];
else if ((A[16] == 1'b1)&&(A[15:12] == 0)&&(A[11:8] == 0)&&(A[3:0] != 0))
Z = blk,blk,sign,A[7:4],A[3:0];
else if ((A[16] == 1'b0)&&(A[15:12] == 0)&&(A[11:8] != 0))
Z = blk,blk,A[11:8],A[7:4],A[3:0];
else if ((A[16] == 1'b1)&&(A[15:12] == 0)&&(A[11:8] != 0))
Z = blk,sign,A[11:8],A[7:4],A[3:0];
else if ((A[16] == 1'b1)&&(A[15:12] != 0))
Z = sign,A[15:12],A[11:8],A[7:4],A[3:0];
else if ((A[16] == 1'b0)&&(A[15:12] != 0))
Z = blk,A[15:12],A[11:8],A[7:4],A[3:0];
else if ((A[16] == 1'b1)&&(A[15:12] == 0)&&(A[11:8] == 0)&&(A[7:4] != 0)&&( A[3:0]== 0))
Z = blk,blk,sign,A[7:4],A[3:0];
else if ((A[16] == 1'b0)&&(A[15:12] == 0)&&(A[11:8] == 0)&&(A[7:4] != 0)&&( A[3:0]== 0))
Z = blk,blk,blk,A[7:4],A[3:0];
else if ((A[16] == 1'b0)&&(A[15:12] == 0)&&(A[11:8] == 0)&&(A[7:4] == 0)&&( A[3:0]== 0))
Z = blk,blk,blk,blk,4'b0;
else
Z = blk,blk,blk,blk,blk;
end
default:
begin Z = blk,blk,blk,blk,blk;
neg,thousands,hundreds,tens,ones = blk,blk,blk,blk,4'b0;
end
endcase
// NEXT STATE LOGIC
initial present = 0;
always@(*)
begin
case(present)
S0: if (( w >= 1) && ( w <=9)) next = S1;
else if (( w == add) || ( w == sub) || ( w == mult) || (w == div)) next = S5;
else if ( w == sign) next = S0;
else if ( w == 0) next = S0;
else next = S0;
S1: if ((w >= 0) && (w <= 9 )) next = S2;
else if ( w == enter) next = S1;
else if ( w==sign) next = S1;
else if(( w == add) || ( w == sub) || ( w == mult) || (w == div)) next = S5;
else next = S1;
S2: if ((w >= 0) && (w <= 9 )) next = S3;
else if ( w == enter) next = S2;
else if ( w==sign) next = S2;
else next = S5;
S3: if ((w >= 0) && (w <= 9 )) next = S4;
else if ( w == enter) next = 3;
else if ( w==sign) next = S3;
else next = S5;
S4: if (( w == add) || ( w == sub) || ( w == mult) || (w == div)) next = S5;
else if ((w == sign)) next = S4;
else if ((w == enter)) next = S4;
else next = S4;
S5: if (( w == add) || ( w == sub) || ( w == mult) || (w == div)) next = S5;
else if ((w >= 0) && (w <= 9 )) next = S6;
else if (( w == enter)) next = S5;
else next = S5;
S6: if (( w >= add) &&(w <= div)) next = S5;
else if ((w >= 0) && (w <= 9 )) next = S7;
else if ((w == sign)) next = S6;
else if ((w == enter)) next = S10;
else next = S6;
S7: if (( w == add) || ( w == sub) || ( w == mult) || (w == div)) next = S5;
else if ((w >= 0) && (w <= 9 )) next = S8;
else if ((w == sign)) next = S7;
else if ((w == enter)) next = S10;
else next = S7;
S8: if (( w == add) || ( w == sub) || ( w == mult) || (w == div)) next = S5;
else if ((w >= 0) && (w <= 9 )) next = S9;
else if ((w == sign)) next = S8;
else if ((w == enter)) next = S10;
else next = S8;
S9: if (( w >= 0)&&( w <= 9)) next = S10;
else if (( w == add) || ( w == sub) || ( w == mult) || (w == div)) next = S5;
else if ((w == sign)) next = S9;
else if ((w == enter)) next = S10;
else next = S9;
S10: if ((w >= 1) && (w <= 9 )) next = S0;
else if (( w == add) || ( w == sub) || ( w == mult) || (w == div)) next = S10;
else if (w == 0) next = S0;
else if ((w >= 1) && (w <= 9 )&&( error == 1'b1)) next = S10;
else next = S10;
default: next = S0;
endcase
end
// STATE TRANSITION FOR CONTROL LOGIC
always@(posedge clock or posedge reset)
if (reset)
present <= S0;
else
present <= next;
// REGISTER TRANFER OPERATIONS
always@(posedge clock or posedge reset)
if (reset)
begin
errordisp <= 0;
ones <= 4'b0;
tens <= 4'b0;
hundreds <= 4'b0;
thousands <= 4'b0;
neg <= 0;
onesB <= 4'b0;
tensB <= 4'b0;
hundredsB <= 4'b0;
thousandsB <= 4'b0;
negB <= 0;
end
else
case(present)
S0:begin
if ((w<=4'b1001) && (w>4'b0000))
begin
tens <= 4'b0;
hundreds <=4'b0;
thousands <= 4'b0;
neg <= 1'b0;
ones <= w;
A <= neg,4'b0,4'b0,4'b0,ones;
end
else if ((w >= add) && ( w <= div))
begin
operand <= w;
ones <= 4'd0;
A <= neg,4'b0,4'b0,4'b0,4'd0;
end
end
S1: begin
if ((w<=4'b1001) && (w>=4'b0000))
begin
tens <= ones;
ones <= w;
A <= neg,4'b0,4'b0,tens,ones;
end
else if (w==4'b1111)
begin
neg <= ~neg;
if (neg == 1)
begin
tens <= sign ;
end
end
else if ((w >= add) && ( w <= div))
begin
A <= neg,4'b0,4'b0,4'b0,ones;
operand <= w;
end
else
begin
tens <= 4'b0;
ones <= ones;
end
end
S2: begin
if ((w<=4'b1001) && (w>=4'b0000))
begin
A <= neg,4'b0,hundreds,tens,ones;
hundreds <= tens;
tens <= ones;
ones <= w;
end
else if (w==4'b1111)
begin
neg <= ~neg;
if (neg ==1)
begin
hundreds <= sign;
end
end
else if ((w >= add) && ( w <= div))
begin
operand <= w;
A <= neg,4'b0,4'b0,tens,ones;
end
end
S3: begin
if ((w<=4'b1001) && (w>=4'b0000))
begin
A <= neg,thousands,hundreds,tens,ones;
thousands <= hundreds;
hundreds <= tens;
tens <= ones;
ones <= w;
end
else if (w==4'b1111)
begin
neg <=~neg;
if (neg ==1)
thousands <= sign;
end
else if ((w >= add) && ( w <= div))
begin
operand <= w;
A <= neg,4'b0,hundreds,tens,ones;
end
end
S4: begin
if (w==4'b1111)
begin
neg <= ~neg;
if (neg == 1)
neg <= sign;
end
else if ((w >= add) && ( w <= div))
begin
operand <= w;
A <= neg,thousands,hundreds,tens,ones;
end
end
S5:
if ((w >= add) && ( w <= div))
begin
A <= answer; operand <= w;
end
else if (( w >= 1)&&( w <= 9))
begin
tensB <= 4'b0;
hundredsB <= 4'b0;
thousandsB <= 4'b0;
onesB <= w;
B <= negB,4'b0,4'b0,4'b0,onesB;
end
else if ( w == 4'b1111)
negB <= ~negB;
S6:
if (( w >= 0)&&( w <= 9))
begin
onesB <= w;
tensB <= onesB;
B <= negB,4'b0,4'b0,tensB,onesB;
end
else if (w == 4'b1111)
begin
negB <= ~negB;
if (neg == 1)
tensB <= sign ;
end
else if (( w >= add )&&( w <= div) &&( error == 1'b0))
begin
operand <= w; A <= answer;
end
else if (( w >= add )&&( w <= div) &&( error == 1'b1))
errordisp <= 1'b1;
else if (( w == enter)&&( error == 1'b0))
begin
A <= answer; operand <= w;
end
else if (( w == enter)&&( error == 1'b1))
errordisp <= 1'b1;
S7:
if (( w >= 0)&&( w <= 9))
begin
hundredsB <= tensB;
onesB <= w;
tensB <= onesB;
B <= negB,4'b0,hundredsB,tensB,onesB;
end
else if (w == 4'b1111)
begin
negB <= ~negB;
if (neg == 1)
hundredsB <= sign ;
end
else if (( w >= add )&&( w <= div) &&( error == 1'b0))
begin
operand <= w; A <= answer;
tens <= answer[7:4];
hundreds <= answer[11:8];
thousands <= answer[15:12];
ones <= answer[3:0];
end
else if (( w >= add )&&( w <= div) &&( error == 1'b1))
errordisp <= 1'b1;
else if (( w == enter)&&( error == 1'b0))
begin
A <= answer; operand <= w;
end
else if (( w == enter)&&( error == 1'b1))
errordisp <= 1'b1;
S8:
if (( w >= 0)&&( w <= 9))
begin
neg <= sign;
thousandsB <= hundredsB;
hundreds <= tensB;
onesB <= w;
tensB <= onesB;
B <= negB,thousandsB,hundredsB,tensB,onesB;
end
else if (w == 4'b1111)
begin
negB <= ~negB;
if (neg == 1)
tensB <= sign ;
end
else if (( w >= add )&&( w <= div) &&( error == 1'b0))
begin
operand <= w; A <= answer;
end
else if (( w >= add )&&( w <= div) &&( error == 1'b1))
errordisp <= 1'b1;
else if (( w == enter)&&( error == 1'b0))
begin
A <= answer; operand <= w;
end
else if (( w == enter)&&( error == 1'b1))
errordisp <= 1'b1;
S9:
if (( w >= 0)&&( w <= 9))
begin
neg <= sign;
thousandsB <= hundredsB;
hundreds <= tensB;
onesB <= w;
tensB <= onesB;
B <= negB,thousandsB,hundredsB,tensB,onesB;
end
else if (( w >= add )&&( w <= div)&&( error == 1'b0))
begin
A <= answer;
operand <= w;
end
else if (w == 4'b1111)
negB <= ~negB;
else if (( w >= add )&&( w <= div)&&( error == 1'b1))
errordisp <= 1'b1;
else if ((w == enter)&&( error == 1'b0))
A <= answer;
else if ((w == enter)&&( error == 1'b1))
errordisp <= 1'b1;
S10:
if (( w >= 10 )&&( w <= div))
operand <= w;
else if (( w >= 0) && (w <= 9)&&(error == 1'b0))
begin
A <= 1'b0,4'b0,4'b0,4'b0,ones;
ones <= w;
end
else if (w == 4'b1111)
neg <= ~neg;
default:
A <= 1'b0,4'b0,4'b0,4'b0,4'b0;
endcase
always@(*)
if (operand == 4'b1010)
Operator = 2'b00;
else if (operand == 4'b1011)
Operator = 2'b01;
else if (operand == 4'b1100)
Operator = 2'b10;
else if (operand == 4'b1101)
Operator = 2'b11;
else
Operator = 2'b00;
//BCDtosigned A1(.BCD(A),.sign2(A2),.negA(neg),.onesA(ones),.tensA(tens),.hundredsA(hundreds),.thousandsA(thousands));
//BCDtosigned B1(.BCD(B),.sign2(B2),.negA(negB),.onesA(onesB),.tensA(tensB),.hundredsA(hundredsB),.thousandsA(thousandsB));
//arithmetic M1(.X(A2),.Y(B2),.Zout(Z1),.Operator(Operator),.Error(error));
//signedtoBCD C1(.BCDG(answer),.sign2(Z1));
endmodule
答案
在你的情况下，多驱动错误意味着你正在对同一个模块进行赋值。reg 来自两个不同 always 块。
例如 ones reg 块中分配 // OUTPUT LOGIC:
neg,thousands,hundreds,tens,ones = blk,blk,blk,blk,4'b0;
也在区块内 // REGISTER TRANFER OPERATIONS，首先是。
ones <= 4'b0;
我之所以能轻易地弄明白这一点 是因为我把你的代码读到了一个源代码浏览器工具里 它有智能，能给我显示一个简短的列表，列出所有的行数，在这个列表里 ones 被驱动（分配）。
如果你使用的工具没有这个功能，那么你可以在你的编辑器中搜索所有代码行中的 ones 是在任务的左侧。
您应该只对相同的人进行任务分配。reg 从单一 always 块。 你需要重新设计你的代码，因为你已经怀疑了。
在未来，你应该发布你得到的确切错误信息。
你的代码还有其他几个基本的Verilog问题，但完整的代码评论是Stack Overflow的题外话。
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