为什么在VHDL中出现此“实体未分析错误”

Question

我正在GHDL中运行我的VHDL代码，并得到这2个错误”类关键字（例如'variable'是可预期的”和“未分析实体文件名”。我什至不知道如何弄清楚正在做什么错误。这是我的代码：

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

use ieee.numeric_std.all;

entity mini1 is

port(   

         Aw: in std_logic_VECTOR(1 downto 0);

         oe: in STD_LOGIC;

         Be: out std_logic_VECTOR(1 downto 0);

         Y: out std_logic_VECTOR(1 downto 0));


end mini1;

ARCHITECTURE maxi OF mini1 is

   SIGNAL  a  : STD_LOGIC_VECTOR(1 downto 0);

   SIGNAL  b  : STD_LOGIC_VECTOR(1 downto 0);

BEGIN 

    PROCESS (oe, Y)          -- Behavioral representation 

        b <= Aw;

        BEGIN                    -- of tri-states.
        IF (oe = '0') THEN
            --Y <= "ZZ";
            Y <= a;
        ELSE
            Y <= b; 
        END IF;
        Be <= a;
    END PROCESS;

END maxi;

如果有人帮忙，将不胜感激