ARM GIC-400 寄存器
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1.简介
GIC-400是用于控制中断的。在cubieboard2 上 的A20芯片采用了这款控制器。
cubieboard2 的GIC控制器 的地址是0x01C80000---0x01C87FFF ,长度等于GIC-400寄存器的长度。
具体的内容如下所示。
以0x01C80000为起始地址,下面给出的是偏移:
|
Reserved 未使用,无用 |
|
|
Distributor 配置器 有用 |
|
|
CPU interfaces CPU接口 有用 |
|
|
Virtual interface control block, for the processor that is performing the access 虚拟化相关,无用 |
|
|
Virtual interface control block, for the processor selected by address bits [11:9] 虚拟化相关,无用 |
|
...
|
Alias for Processor 0 Alias for Processor 1 ... Alias for Processor 7 |
|
|
Virtual CPU interfaces 虚拟化相关,无用 |
常用的是图中第二块和第三块,0x1000~0x3fff这部分的配置。
2.Distributor 配置器
distributor这块寄存器的地址 = GIC控制器 的地址 + 0x1000 ,使用的时候别忘记了偏移。然后从这里开始,有如下的寄存器
偏移 |
名称 |
可读写 |
复位后 |
作用 |
---|---|---|---|---|
|
GICD_CTLR |
RW |
|
Distributor Control Register 写入1使能控制器,必备 |
|
GICD_TYPER |
RO |
Configuration-dependent[d] |
Interrupt Controller Type Register 其中可以查看中断线的总数 |
|
GICD_IIDR |
RO |
|
Distributor Implementer Identification Register, GICD_IIDR 存了一些版本信息,没用 |
|
GICD_IGROUPRn |
RW |
|
Interrupt Group Registers[e] 一个位图,控制中断属于A组还是B组 |
|
GICD_ISENABLERn |
RW[f] |
SGIs and PPIs: |
Interrupt Set-Enable Registers 一个位图,用于使能各个中断,写入1使能。有用 |
|
SPIs: |
|||
|
GICD_ICENABLERn |
RW[f] |
|
Interrupt Clear-Enable Registers 和上一个寄存器类似,作用相反,写入1禁止。 |
|
|
|||
|
GICD_ISPENDRn |
RW |
|
Interrupt Set-Pending Registers pend位图,写入1可以进入pend状态 |
|
GICD_ICPENDRn |
RW |
|
Interrupt Clear-Pending Registers 同上,写入1效果相反,阻止pend状态 |
|
GICD_ISACTIVERn |
RW |
|
Interrupt Set-Active Registers 位图,写入1可以激活中断 |
0x380 -0x3BC |
GICD_ICACTIVERn |
RW |
|
Interrupt Clear-Active Registers 写入1反激活中断 |
|
GICD_IPRIORITYRn |
RW |
|
Interrupt Priority Registers 存着各个中断的优先级,每8位算一个 |
|
GICD_ITARGETSRn |
RO[h] |
- |
Interrupt Processor Targets Registers[i] 某个中断应该发往哪个处理器进行处理 |
|
RW |
|
||
|
GICD_ICFGRn |
RO |
SGIs: |
Interrupt Configuration Registers, GICD_ICFGRn 配置中断是低电平触发还是下降沿触发 |
|
RO |
PPIs: |
||
|
RW[j] |
SPIs: |
||
0xD00 |
GICD_PPISR |
RO |
0x00000000 |
Private Peripheral Interrupt Status Register, GICD_PPISR 一般没用 |
0xD04 -0xD3C |
GICD_SPISRn |
RO |
0x00000000 |
Shared Peripheral Interrupt Status Registers, GICD_SPISRn 没用 |
0xF00 |
GICD_SGIR |
WO |
- |
Software Generated Interrupt Register 控制软中断 |
0xF10-0xF1C |
GICD_CPENDSGIRn |
RW |
|
SGI Clear-Pending Registers 软中断的pend位 |
|
GICD_SPENDSGIRn |
RW |
|
SGI Set-Pending Registers 同上,不过写入1时停止pend |
|
GICD_PIDR4 |
RO |
|
Peripheral ID 4 Register |
|
GICD_PIDR5 |
RO |
|
Peripheral ID 5 Register |
|
GICD_PIDR6 |
RO |
|
Peripheral ID 6 Register |
|
GICD_PIDR7 |
RO |
|
Peripheral ID 7 Register |
|
GICD_PIDR0 |
RO |
|
Peripheral ID 0 Register |
|
GICD_PIDR1 |
RO |
|
Peripheral ID 1 Register |
|
GICD_PIDR2 |
RO |
|
Peripheral ID 2 Register |
|
GICD_PIDR3 |
RO |
|
Peripheral ID 3 Register |
|
GICD_CIDR0 |
RO |
|
Component ID 0 Register |
|
GICD_CIDR1 |
RO |
0x000000F0 |
Component ID 1 Register |
|
GICD_CIDR2 |
RO |
|
Component ID 2 Register |
|
GICD_CIDR3 |
RO |
|
Component ID 3 Register |
3.cpu接口
开始地址的偏移量为
Offset |
Name |
Type |
Reset |
Description[a] |
---|---|---|---|---|
|
GICC_CTLR |
RW |
|
CPU Interface Control Register 使能位。写入1使能 |
|
GICC_PMR |
RW |
|
Interrupt Priority Mask Register 限制中断最低优先级,高于此值无法中断,最好写大一点 |
|
GICC_BPR |
RW |
|
Binary Point Register The minimum value of the Binary Point Register depends on which security-banked copy is considered:
|
|
GICC_IAR |
RO |
|
Interrupt Acknowledge Register 只读,中断id |
|
GICC_EOIR |
WO |
- |
End of Interrupt Register 写入以告知cpu已经处理完中断 |
|
GICC_RPR |
RO |
|
Running Priority Register 当前中断优先级 |
|
GICC_HPPIR |
RO |
|
Highest Priority Pending Interrupt Register [c] 最高优先级中断号及其pend值 |
|
GICC_ABPR |
RW |
|
Aliased Binary Point Register[d] The minimum value of the Aliased Binary Point Register is 别名寄存器 |
|
GICC_AIAR |
RO |
|
Aliased Interrupt Acknowledge Register[d] 别名寄存器 |
|
GICC_AEOIR |
WO |
- |
Aliased End of Interrupt Register[d] 别名寄存器 |
|
GICC_AHPPIR |
RO |
|
Aliased Highest Priority Pending Interrupt Register[c][d] 别名寄存器 |
|
GICC_APR0 |
RW |
|
Active Priority Register 用于保存和恢复 |
|
GICC_NSAPR0 |
RW |
|
Non-Secure Active Priority Register[d] 用于保存和恢复 |
|
GICC_IIDR |
RO |
|
CPU Interface Identification Register, GICC_IIDR 存着版本信息 |
|
GICC_DIR |
WO |
- |
Deactivate Interrupt Register |
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