在vcs中编译及运行测试E203例子
Posted mikewolf2002
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E203的Makefile默认是调用 iverilog编译rtl，我们可以做如下修改，使其支持vcs编译。
1. 首先修改e200_opensource/tb/tb_top.v， 增加dump波形的两行代码，这样如果指定DUMPWAVE不等于0，就会打印dump出波形文件。
initial begin
$value$plusargs("DUMPWAVE=%d",dumpwave);
if(dumpwave != 0)begin
// To add your waveform generation function
$fsdbDumpfile("dump.fsdb");
$fsdbDumpvars("+all");
end
end2.修改e200_opensource/vsim/bin/run.makefile, 把SIM_TOOL,SIM_OPTIONS,WAVE_TOOL,WAVE_OPTIONS这些选项为vcs和verdi
RUN_DIR := $PWD TESTCASE := $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32ui-p-addi DUMPWAVE := 1 VSRC_DIR := $RUN_DIR/../install/rtl VTB_DIR := $RUN_DIR/../install/tb TESTNAME := $(notdir $(patsubst %.dump,%,$TESTCASE.dump)) TEST_RUNDIR := $TESTNAME RTL_V_FILES := $(wildcard $VSRC_DIR/*/*.v) TB_V_FILES := $(wildcard $VTB_DIR/*.v) # The following portion is depending on the EDA tools you are using, Please add them by yourself according to your EDA vendors SIM_TOOL := vcs #To-ADD: to add the simulatoin tool #SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code SIM_OPTIONS := -full64 -line +vcsd +vpi -r +plusarg_save -Mupdate +cli+3 +error+10 +v2k +ntb_exit_on_error=10 -negdelay +neg_tchk +memcbk +sdrverbose -timescale=1ns/100ps +warn=all +warn=noTFIPC +warn=noWSUM -sverilog -l vcs.log -LDFLAGS -rdynamic -P $NOVAS_HOME/share/PLI/VCS/linux64/novas_new_dumper.tab $NOVAS_HOME/share/PLI/VCS/linux64/pli.a +incdir+$VSRC_DIR/core/+$VSRC_DIR/perips/ #To-ADD: to add the simulatoin tool options #SIM_OPTIONS := -o vvp.exec -I "$VSRC_DIR/core/" -I "$VSRC_DIR/perips/" -D DISABLE_SV_ASSERTION=1 -g2005 # This is a free solution here to use iverilog to compile the code. Please NOTE!!!! # # Note: # Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded # assertion in the RTL code because iverilog cannot support that syntax, if you # use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION". # # Here we didnt add macro "ENABLE_TB_FORCE" # that macro was used to enable the random interrupt and bus-error insertion to make # more intensive test in e200_opensource/tb/tb_top.v. # Although the test become more intensive, the drawback is it makes the regression # simulation running very slower, so by default now it is turned off. # If you want to turn on them without caring the the regression speed, # you can just add macro `ENABLE_TB_FORCE` here in command line. SIM_EXEC := ../simv #To-ADD: to add the simulatoin executable #SIM_EXEC := vvp $RUN_DIR/vvp.exec -none # The free vvp is tooooo slow to run, so just comment it out, and replaced with the fake way below #SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command WAV_TOOL := verdi #To-ADD: to add the waveform tool WAV_OPTIONS := -2001 -sv -top tb_top +incdir+$VSRC_DIR/core/+$VSRC_DIR/perips/ #To-ADD: to add the waveform tool options WAV_PFIX := #To-ADD: to add the waveform file postfix all: run compile.flg: $RTL_V_FILES $TB_V_FILES @-rm -rf compile.flg $SIM_TOOL $SIM_OPTIONS $RTL_V_FILES $TB_V_FILES ; touch compile.flg compile: compile.flg wave: # gvim -p $TESTCASE.spike.log $TESTCASE.dump & $WAV_TOOL $WAV_OPTIONS $RTL_V_FILES $TB_V_FILES & run: compile rm -rf $TEST_RUNDIR mkdir $TEST_RUNDIR cd $TEST_RUNDIR; $SIM_EXEC +DUMPWAVE=$DUMPWAVE +TESTCASE=$TESTCASE |& tee $TESTNAME.log; cd $RUN_DIR; .PHONY: run clean all
3. cd e200_opensource/vsim, 执行make install CORE,
执行make install，则会在e200_opensource/vsim目录下，创建install目录，并把testbench文件和rtl文件copy到install目录，并把testbench文件tb_top.v中的e200,替换为core_name,E200替换为CORE_NAME,也就是e203。
SIM_DIR := $PWD RUN_DIR := $PWD/run TESTNAME := rv32ui-p-add TESTCASE := $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/$TESTNAME DUMPWAVE := 1 CORE := e203 CFG := $CORE_config E201 := e201 E203 := e203 E205 := e205 E205F := e205f E205FD := e205fd E225FD := e225fd CORE_NAME = $(shell echo $(CORE) | tr a-z A-Z) core_name = $(shell echo $(CORE) | tr A-Z a-z) all: run_test install: mkdir -p $SIM_DIR/install/tb cp $SIM_DIR/../tb/tb_top.v $SIM_DIR/install/tb/ -rf sed -i "s/e200/$core_name/g" $SIM_DIR/install/tb/tb_top.v sed -i "s/E200/$CORE_NAME/g" $SIM_DIR/install/tb/tb_top.v cp $SIM_DIR/../rtl/$core_name $SIM_DIR/install/rtl -rf $RUN_DIR: mkdir -p $RUN_DIR rm -f $RUN_DIR/Makefile ln -s $SIM_DIR/bin/run.makefile $RUN_DIR/Makefile compile: $RUN_DIR make compile RUN_DIR=$RUN_DIR -C $RUN_DIR wave: $RUN_DIR make wave TESTCASE=$TESTCASE RUN_DIR=$RUN_DIR -C $RUN_DIR run_test: compile make run DUMPWAVE=$DUMPWAVE TESTCASE=$TESTCASE RUN_DIR=$RUN_DIR -C $RUN_DIR SELF_TESTS := $(patsubst %.dump,%,$(wildcard $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32uc-p*.dump)) ifeq ($(core_name),$E203) SELF_TESTS += $(patsubst %.dump,%,$(wildcard $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32um-p*.dump)) SELF_TESTS += $(patsubst %.dump,%,$(wildcard $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32ua-p*.dump)) endif ifeq ($(core_name),$E205) SELF_TESTS += $(patsubst %.dump,%,$(wildcard $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32um-p*.dump)) SELF_TESTS += $(patsubst %.dump,%,$(wildcard $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32ua-p*.dump)) endif ifeq ($(core_name),$E205F) SELF_TESTS += $(patsubst %.dump,%,$(wildcard $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32um-p*.dump)) SELF_TESTS += $(patsubst %.dump,%,$(wildcard $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32ua-p*.dump)) SELF_TESTS += $(patsubst %.dump,%,$(wildcard $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32uf-p*.dump)) endif ifeq ($(core_name),$E205FD) SELF_TESTS += $(patsubst %.dump,%,$(wildcard $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32um-p*.dump)) SELF_TESTS += $(patsubst %.dump,%,$(wildcard $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32ua-p*.dump)) SELF_TESTS += $(patsubst %.dump,%,$(wildcard $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32ud-p*.dump)) SELF_TESTS += $(patsubst %.dump,%,$(wildcard $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32uf-p*.dump)) endif ifeq ($(core_name),$E225FD) SELF_TESTS += $(patsubst %.dump,%,$(wildcard $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32um-p*.dump)) SELF_TESTS += $(patsubst %.dump,%,$(wildcard $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32ua-p*.dump)) SELF_TESTS += $(patsubst %.dump,%,$(wildcard $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32ud-p*.dump)) SELF_TESTS += $(patsubst %.dump,%,$(wildcard $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32uf-p*.dump)) endif SELF_TESTS += $(patsubst %.dump,%,$(wildcard $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32ui-p*.dump)) SELF_TESTS += $(patsubst %.dump,%,$(wildcard $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32mi-p*.dump)) regress_prepare: make compile @-rm -rf $RUN_DIR/rv32*.log regress_run: $(foreach tst,$(SELF_TESTS), make run_test DUMPWAVE=0 TESTCASE=$(tst);) regress_collect: @-rm -rf $RUN_DIR/regress.res @find $RUN_DIR -name "rv32*.log" -exec bin/find_test_fail.csh >> $RUN_DIR/regress.res \; @cat $RUN_DIR/regress.res regress: regress_prepare regress_run regress_collect clean: rm -rf run rm -rf install .PHONY: compile run install clean all run_test regress regress_prepare regress_run regress_collect
4. 在目录e200_opensource/vsim执行make compile
这是会执行以下的flow，会创建run目录，并链接run/Makefile到bin/run.makefile，这个时候执行make compile
$RUN_DIR: mkdir -p $RUN_DIR rm -f $RUN_DIR/Makefile ln -s $SIM_DIR/bin/run.makefile $RUN_DIR/Makefile compile: $RUN_DIR make compile RUN_DIR=$RUN_DIR -C $RUN_DIR
就是在run目录下执行Makefile文件中的make all,编译rtl代码和testbench文件。
all: run compile.flg: $RTL_V_FILES $TB_V_FILES @-rm -rf compile.flg $SIM_TOOL $SIM_OPTIONS $RTL_V_FILES $TB_V_FILES ; touch compile.flg
５. 在e200_opensource/vsim目录里下执行make run_test, 则会调用以下flow,默认会run testcase rv32ui-p-add
run_test: compile
make run DUMPWAVE=$DUMPWAVE TESTCASE=$TESTCASE RUN_DIR=$RUN_DIR -C $RUN_DIRcd $TEST_RUNDIR; $SIM_EXEC +DUMPWAVE=$DUMPWAVE +TESTCASE=$TESTCASE |& tee $TESTNAME.log; cd $RUN_DIR;
此时run目录下会有rv32ui-p-add目录，里面会有波形文件和log文件。
６. 在e200_opensource/vsim目录里下执行 make run_test TESTNAME=rv32ui-p-and, 此时run目录下会有rv32ui-p-and目录，里面会有波形文件和log文件。
7. 在e200_opensource/vsim目录里下执行 make wave,则会在verdi中打开rtl文件，然后打开相应test的波形文件，就可以就行调试程序了。
８.我们对Makefile进行一点改动，用make debug TESTCASE=rv32ui-p-and 就可以同时打开design和波形了。
e200_opensource/vsim/Makefile, 增加debug部分。
wave: $RUN_DIR make wave TESTCASE=$TESTCASE RUN_DIR=$RUN_DIR -C $RUN_DIR debug: $RUN_DIR make debug TESTCASE=$TESTCASE RUN_DIR=$RUN_DIR -C $RUN_DIR run_test: compile make run DUMPWAVE=$DUMPWAVE TESTCASE=$TESTCASE RUN_DIR=$RUN_DIR -C $RUN_DIR
e200_opensource/vsim/run/Makefile, 增加debug部分。
RUN_DIR := $PWD TESTCASE := $RUN_DIR/../../riscv-tools/riscv-tests/isa/generated/rv32ui-p-addi DUMPWAVE := 1 VSRC_DIR := $RUN_DIR/../install/rtl VTB_DIR := $RUN_DIR/../install/tb TESTNAME := $(notdir $(patsubst %.dump,%,$TESTCASE.dump)) TEST_RUNDIR := $TESTNAME RTL_V_FILES := $(wildcard $VSRC_DIR/*/*.v) TB_V_FILES := $(wildcard $VTB_DIR/*.v) WAVE_FILE := $RUN_DIR/$TESTNAME/dump.fsdb # The following portion is depending on the EDA tools you are using, Please add them by yourself according to your EDA vendors SIM_TOOL := vcs #To-ADD: to add the simulatoin tool #SIM_TOOL := iverilog # this is a free solution here to use iverilog to compile the code SIM_OPTIONS := -full64 -line +vcsd +vpi -r +plusarg_save -Mupdate +cli+3 +error+10 +v2k +ntb_exit_on_error=10 -negdelay +neg_tchk +memcbk +sdrverbose -timescale=1ns/100ps +warn=all +warn=noTFIPC +warn=noWSUM -sverilog -l vcs.log -LDFLAGS -rdynamic -P $NOVAS_HOME/share/PLI/VCS/linux64/novas_new_dumper.tab $NOVAS_HOME/share/PLI/VCS/linux64/pli.a +incdir+$VSRC_DIR/core/+$VSRC_DIR/perips/ #To-ADD: to add the simulatoin tool options #SIM_OPTIONS := -o vvp.exec -I "$VSRC_DIR/core/" -I "$VSRC_DIR/perips/" -D DISABLE_SV_ASSERTION=1 -g2005 # This is a free solution here to use iverilog to compile the code. Please NOTE!!!! # # Note: # Here we add a macro "DISABLE_SV_ASSERTION" to disable the system-verilog coded # assertion in the RTL code because iverilog cannot support that syntax, if you # use other EDA tools which support the systemverilog, you should not add this macro "DISABLE_SV_ASSERTION". # # Here we didnt add macro "ENABLE_TB_FORCE" # that macro was used to enable the random interrupt and bus-error insertion to make # more intensive test in e200_opensource/tb/tb_top.v. # Although the test become more intensive, the drawback is it makes the regression # simulation running very slower, so by default now it is turned off. # If you want to turn on them without caring the the regression speed, # you can just add macro `ENABLE_TB_FORCE` here in command line. SIM_EXEC := ../simv #To-ADD: to add the simulatoin executable #SIM_EXEC := vvp $RUN_DIR/vvp.exec -none # The free vvp is tooooo slow to run, so just comment it out, and replaced with the fake way below #SIM_EXEC := echo "Test Result Summary: PASS" # This is a fake run to just direct print PASS info to the log, the user need to actually replace it to the real EDA command WAV_TOOL := verdi #To-ADD: to add the waveform tool WAV_OPTIONS := -2001 -sv -top tb_top +incdir+$VSRC_DIR/core/+$VSRC_DIR/perips/ #To-ADD: to add the waveform tool options WAV_PFIX := #To-ADD: to add the waveform file postfix all: run compile.flg: $RTL_V_FILES $TB_V_FILES @-rm -rf compile.flg $SIM_TOOL $SIM_OPTIONS $RTL_V_FILES $TB_V_FILES ; touch compile.flg compile: compile.flg wave: # gvim -p $TESTCASE.spike.log $TESTCASE.dump & $WAV_TOOL $WAV_OPTIONS $RTL_V_FILES $TB_V_FILES & debug: $WAV_TOOL $WAV_OPTIONS $RTL_V_FILES $TB_V_FILES -ssf $WAVE_FILE run: compile rm -rf $TEST_RUNDIR mkdir $TEST_RUNDIR cd $TEST_RUNDIR; $SIM_EXEC +DUMPWAVE=$DUMPWAVE +TESTCASE=$TESTCASE |& tee $TESTNAME.log; cd $RUN_DIR; .PHONY: run clean all
９. 在e200_opensource/vsim目录里下执行make regress_run CORE=e203, 则会运行所有的testcase，进行回归测试。
10. 在e200_opensource/vsim目录里下执行make regress_collect CORE=e203, 则会比较所有的testcase结果，如果test pass，则打印PASS,失败，则打印FAIL
11. 在e200_opensource/vsim目录里下执行make clean, 则会删除install和run目录。
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