单片机成长之路（51基础篇） - 023 N76e003 系统时钟切换到外部时钟
Posted jikexianfeng
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N76e003切换到外部时钟的资料很少(因为N76e003的片子是不支持无源晶振的，有源晶振的成本又很高，所以网上很少有对N76e003的介绍)。有图有真相：
代码如下：
main.c
1 #include <N76E003.H> 2 #include <SFR_Macro.h> 3 #include <Function_Define.h> 4 5 bit BIT_TMP; // 调用 SFR_Macro.h 使用的 6 7 void main(void) 8 // 开通外部 9 set_EXTEN1; 10 set_EXTEN0; 11 // 等待外部稳定 12 while(!(CKSWT|0x08)); 13 // 选择外部时钟 14 clr_OSC1; 15 set_OSC0; 16 // 等待外部时钟切换成功 17 while(CKEN&0x01); 18 while(1) 19 ; // 函数主题 20 21
1 /*-------------------------------------------------------------------------- 2 N76E003.H 3 4 Header file for Nuvoton N76E003 5 --------------------------------------------------------------------------*/ 6 7 #ifndef __N76E885_H__ 8 #define __N76E885_H__ 9 10 sfr P0 = 0x80; 11 sfr SP = 0x81; 12 sfr DPL = 0x82; 13 sfr DPH = 0x83; 14 sfr RWK = 0x86; 15 sfr PCON = 0x87; 16 17 sfr TCON = 0x88; 18 sfr TMOD = 0x89; 19 sfr TL0 = 0x8A; 20 sfr TL1 = 0x8B; 21 sfr TH0 = 0x8C; 22 sfr TH1 = 0x8D; 23 sfr CKCON = 0x8E; 24 sfr WKCON = 0x8F; 25 26 sfr P1 = 0x90; 27 sfr SFRS = 0x91; //TA Protection 28 sfr CAPCON0 = 0x92; 29 sfr CAPCON1 = 0x93; 30 sfr CAPCON2 = 0x94; 31 sfr CKDIV = 0x95; 32 sfr CKSWT = 0x96; //TA Protection 33 sfr CKEN = 0x97; //TA Protection 34 35 sfr SCON = 0x98; 36 sfr SBUF = 0x99; 37 sfr SBUF_1 = 0x9A; 38 sfr EIE = 0x9B; 39 sfr EIE1 = 0x9C; 40 sfr CHPCON = 0x9F; //TA Protection 41 42 sfr P2 = 0xA0; 43 sfr AUXR1 = 0xA2; 44 sfr BODCON0 = 0xA3; //TA Protection 45 sfr IAPTRG = 0xA4; //TA Protection 46 sfr IAPUEN = 0xA5; //TA Protection 47 sfr IAPAL = 0xA6; 48 sfr IAPAH = 0xA7; 49 50 sfr IE = 0xA8; 51 sfr SADDR = 0xA9; 52 sfr WDCON = 0xAA; //TA Protection 53 sfr BODCON1 = 0xAB; //TA Protection 54 sfr P3M1 = 0xAC; 55 sfr P3S = 0xAC; //Page1 56 sfr P3M2 = 0xAD; 57 sfr P3SR = 0xAD; //Page1 58 sfr IAPFD = 0xAE; 59 sfr IAPCN = 0xAF; 60 61 sfr P3 = 0xB0; 62 sfr P0M1 = 0xB1; 63 sfr P0S = 0xB1; //Page1 64 sfr P0M2 = 0xB2; 65 sfr P0SR = 0xB2; //Page1 66 sfr P1M1 = 0xB3; 67 sfr P1S = 0xB3; //Page1 68 sfr P1M2 = 0xB4; 69 sfr P1SR = 0xB4; //Page1 70 sfr P2S = 0xB5; 71 sfr IPH = 0xB7; 72 sfr PWMINTC = 0xB7; //Page1 73 74 sfr IP = 0xB8; 75 sfr SADEN = 0xB9; 76 sfr SADEN_1 = 0xBA; 77 sfr SADDR_1 = 0xBB; 78 sfr I2DAT = 0xBC; 79 sfr I2STAT = 0xBD; 80 sfr I2CLK = 0xBE; 81 sfr I2TOC = 0xBF; 82 83 sfr I2CON = 0xC0; 84 sfr I2ADDR = 0xC1; 85 sfr ADCRL = 0xC2; 86 sfr ADCRH = 0xC3; 87 sfr T3CON = 0xC4; 88 sfr PWM4H = 0xC4; //Page1 89 sfr RL3 = 0xC5; 90 sfr PWM5H = 0xC5; //Page1 91 sfr RH3 = 0xC6; 92 sfr PIOCON1 = 0xC6; //Page1 93 sfr TA = 0xC7; 94 95 sfr T2CON = 0xC8; 96 sfr T2MOD = 0xC9; 97 sfr RCMP2L = 0xCA; 98 sfr RCMP2H = 0xCB; 99 sfr TL2 = 0xCC; 100 sfr PWM4L = 0xCC; //Page1 101 sfr TH2 = 0xCD; 102 sfr PWM5L = 0xCD; //Page1 103 sfr ADCMPL = 0xCE; 104 sfr ADCMPH = 0xCF; 105 106 sfr PSW = 0xD0; 107 sfr PWMPH = 0xD1; 108 sfr PWM0H = 0xD2; 109 sfr PWM1H = 0xD3; 110 sfr PWM2H = 0xD4; 111 sfr PWM3H = 0xD5; 112 sfr PNP = 0xD6; 113 sfr FBD = 0xD7; 114 115 sfr PWMCON0 = 0xD8; 116 sfr PWMPL = 0xD9; 117 sfr PWM0L = 0xDA; 118 sfr PWM1L = 0xDB; 119 sfr PWM2L = 0xDC; 120 sfr PWM3L = 0xDD; 121 sfr PIOCON0 = 0xDE; 122 sfr PWMCON1 = 0xDF; 123 124 sfr ACC = 0xE0; 125 sfr ADCCON1 = 0xE1; 126 sfr ADCCON2 = 0xE2; 127 sfr ADCDLY = 0xE3; 128 sfr C0L = 0xE4; 129 sfr C0H = 0xE5; 130 sfr C1L = 0xE6; 131 sfr C1H = 0xE7; 132 133 sfr ADCCON0 = 0xE8; 134 sfr PICON = 0xE9; 135 sfr PINEN = 0xEA; 136 sfr PIPEN = 0xEB; 137 sfr PIF = 0xEC; 138 sfr C2L = 0xED; 139 sfr C2H = 0xEE; 140 sfr EIP = 0xEF; 141 142 sfr B = 0xF0; 143 sfr CAPCON3 = 0xF1; 144 sfr CAPCON4 = 0xF2; 145 sfr SPCR = 0xF3; 146 sfr SPCR2 = 0xF3; //Page1 147 sfr SPSR = 0xF4; 148 sfr SPDR = 0xF5; 149 sfr AINDIDS = 0xF6; 150 sfr EIPH = 0xF7; 151 152 sfr SCON_1 = 0xF8; 153 sfr PDTEN = 0xF9; //TA Protection 154 sfr PDTCNT = 0xFA; //TA Protection 155 sfr PMEN = 0xFB; 156 sfr PMD = 0xFC; 157 sfr EIP1 = 0xFE; 158 sfr EIPH1 = 0xFF; 159 160 /* BIT Registers */ 161 /* SCON_1 */ 162 sbit SM0_1 = SCON_1^7; 163 sbit FE_1 = SCON_1^7; 164 sbit SM1_1 = SCON_1^6; 165 sbit SM2_1 = SCON_1^5; 166 sbit REN_1 = SCON_1^4; 167 sbit TB8_1 = SCON_1^3; 168 sbit RB8_1 = SCON_1^2; 169 sbit TI_1 = SCON_1^1; 170 sbit RI_1 = SCON_1^0; 171 172 /* ADCCON0 */ 173 sbit ADCF = ADCCON0^7; 174 sbit ADCS = ADCCON0^6; 175 sbit ETGSEL1 = ADCCON0^5; 176 sbit ETGSEL0 = ADCCON0^4; 177 sbit ADCHS3 = ADCCON0^3; 178 sbit ADCHS2 = ADCCON0^2; 179 sbit ADCHS1 = ADCCON0^1; 180 sbit ADCHS0 = ADCCON0^0; 181 182 /* PWMCON0 */ 183 sbit PWMRUN = PWMCON0^7; 184 sbit LOAD = PWMCON0^6; 185 sbit PWMF = PWMCON0^5; 186 sbit CLRPWM = PWMCON0^4; 187 188 189 /* PSW */ 190 sbit CY = PSW^7; 191 sbit AC = PSW^6; 192 sbit F0 = PSW^5; 193 sbit RS1 = PSW^4; 194 sbit RS0 = PSW^3; 195 sbit OV = PSW^2; 196 sbit P = PSW^0; 197 198 /* T2CON */ 199 sbit TF2 = T2CON^7; 200 sbit TR2 = T2CON^2; 201 sbit CM_RL2 = T2CON^0; 202 203 /* I2CON */ 204 sbit I2CEN = I2CON^6; 205 sbit STA = I2CON^5; 206 sbit STO = I2CON^4; 207 sbit SI = I2CON^3; 208 sbit AA = I2CON^2; 209 sbit I2CPX = I2CON^0; 210 211 /* IP */ 212 sbit PADC = IP^6; 213 sbit PBOD = IP^5; 214 sbit PS = IP^4; 215 sbit PT1 = IP^3; 216 sbit PX1 = IP^2; 217 sbit PT0 = IP^1; 218 sbit PX0 = IP^0; 219 220 /* P3 */ 221 sbit P30 = P3^0; 222 223 /* IE */ 224 sbit EA = IE^7; 225 sbit EADC = IE^6; 226 sbit EBOD = IE^5; 227 sbit ES = IE^4; 228 sbit ET1 = IE^3; 229 sbit EX1 = IE^2; 230 sbit ET0 = IE^1; 231 sbit EX0 = IE^0; 232 233 /* P2 */ 234 sbit P20 = P2^0; 235 236 /* SCON */ 237 sbit SM0 = SCON^7; 238 sbit FE = SCON^7; 239 sbit SM1 = SCON^6; 240 sbit SM2 = SCON^5; 241 sbit REN = SCON^4; 242 sbit TB8 = SCON^3; 243 sbit RB8 = SCON^2; 244 sbit TI = SCON^1; 245 sbit RI = SCON^0; 246 247 /* P1 */ 248 sbit P17 = P1^7; 249 sbit AIN0 = P1^7; 250 251 sbit P10 = P1^0; 252 sbit PWM0 = P1^0; 253 sbit P11 = P1^1; 254 sbit PWM1 = P1^1; 255 sbit P12 = P1^2; 256 257 /* TCON */ 258 sbit TF1 = TCON^7; 259 sbit TR1 = TCON^6; 260 sbit TF0 = TCON^5; 261 sbit TR0 = TCON^4; 262 sbit IE1 = TCON^3; 263 sbit IT1 = TCON^2; 264 sbit IE0 = TCON^1; 265 sbit IT0 = TCON^0; 266 267 /* P0 */ 268 sbit P00 = P0^0; 269 sbit INT0 = P0^0; 270 sbit VREF = P0^0; 271 272 sbit P01 = P0^1; 273 sbit INT1 = P0^1; 274 sbit AIN1 = P0^1; 275 276 sbit P02 = P0^2; 277 sbit PWM2 = P0^2; 278 sbit AIN2 = P0^2; 279 280 sbit P03 = P0^3; 281 sbit PWM3 = P0^3; 282 sbit TXD = P0^3; 283 sbit AIN3 = P0^3; 284 285 sbit P04 = P0^4; 286 sbit SS = P0^4; 287 sbit AIN4 = P0^4; 288 289 sbit P05 = P0^5; 290 sbit PWM4 = P0^5; 291 sbit SPICK = P0^5; 292 sbit AIN5 = P0^5; 293 294 sbit P06 = P0^6; 295 sbit SCL = P0^6; 296 sbit AIN6 = P0^6; 297 sbit PWM5 = P0^6; 298 299 sbit P07 = P0^7; 300 sbit AIN7 = P0^7; 301 sbit PWM6 = P0^7; 302 303 304 #endif
1 /**** P0 80H *****/ 2 #define set_P00 P00 = 1 3 #define set_P01 P01 = 1 4 #define set_P02 P02 = 1 5 #define set_P03 P03 = 1 6 #define set_P04 P04 = 1 7 #define set_P05 P05 = 1 8 #define set_P06 P06 = 1 9 #define set_P07 P07 = 1 10 11 #define clr_P00 P00 = 0 12 #define clr_P01 P01 = 0 13 #define clr_P02 P02 = 0 14 #define clr_P03 P03 = 0 15 #define clr_P04 P04 = 0 16 #define clr_P05 P05 = 0 17 #define clr_P06 P06 = 0 18 #define clr_P07 P07 = 0 19 20 //**** SP 81H **** 21 //**** DPH 82H **** 22 //**** DPL 83H **** 23 //**** RWK 86H **** 24 25 //**** PCON 87H ***** 26 #define set_SMOD PCON |= SET_BIT7 27 #define set_SMOD0 PCON |= SET_BIT6 28 #define set_POF PCON |= SET_BIT4 29 #define set_GF1 PCON |= SET_BIT3 30 #define set_GF0 PCON |= SET_BIT2 31 #define set_PD PCON |= SET_BIT1 32 #define set_IDL PCON |= SET_BIT0 33 34 #define clr_SMOD PCON &= ~SET_BIT7 35 #define clr_SMOD0 PCON &= ~SET_BIT6 36 #define clr_POF PCON &= ~SET_BIT4 37 #define clr_GF1 PCON &= ~SET_BIT3 38 #define clr_GF0 PCON &= ~SET_BIT2 39 #define clr_PD PCON &= ~SET_BIT1 40 #define clr_IDL PCON &= ~SET_BIT0 41 42 /**** TCON 88H ****/ 43 #define set_TF1 TF1 = 1 44 #define set_TR1 TR1 = 1 45 #define set_TF0 TF0 = 1 46 #define set_TR0 TR0 = 1 //启动定时器0(定时器0启动控制,0定时器0终止，清除该位将终止定时器0并且当前计数值将保存到TH0和TL0中，1使能定时器0) 47 #define set_IE1 IE1 = 1 48 #define set_IT1 IT1 = 1 49 #define set_IE0 IE0 = 1 50 #define set_IT0 IT0 = 1 51 52 #define clr_TF1 TF1 = 0 53 #define clr_TR1 TR1 = 0 54 #define clr_TF0 TF0 = 0 55 #define clr_TR0 TR0 = 0 56 #define clr_IE1 IE1 = 0 57 #define clr_IT1 IT1 = 0 58 #define clr_IE0 IE0 = 0 59 #define clr_IT0 IT0 = 0 60 61 //**** TMOD 89H **** 62 #define set_GATE_T1 TMOD |= SET_BIT7 63 #define set_CT_T1 TMOD |= SET_BIT6 64 #define set_M1_T1 TMOD |= SET_BIT5 65 #define set_M0_T1 TMOD |= SET_BIT4 66 #define set_GATE_T0 TMOD |= SET_BIT3 67 #define set_CT_T0 TMOD |= SET_BIT2 68 #define set_M1_T0 TMOD |= SET_BIT1 69 #define set_M0_T0 TMOD |= SET_BIT0 70 71 #define clr_GATE_T1 TMOD &= ~SET_BIT7 72 #define clr_CT_T1 TMOD &= ~SET_BIT6 73 #define clr_M1_T1 TMOD &= ~SET_BIT5 74 #define clr_M0_T1 TMOD &= ~SET_BIT4 75 #define clr_GATE_T0 TMOD &= ~SET_BIT3 76 #define clr_CT_T0 TMOD &= ~SET_BIT2 77 #define clr_M1_T0 TMOD &= ~SET_BIT1 78 #define clr_M0_T0 TMOD &= ~SET_BIT0 79 80 //**** TH1 8AH **** 81 //**** TH0 8BH **** 82 //**** TL1 8CH **** 83 //**** TL0 8DH **** 84 85 //CKCON - 8EH 时钟控制寄存器 86 #define set_PWMCKS CKCON |= SET_BIT6 //设置pwm时钟源为定时器1的溢出(0为系统时钟，1为定时器1的溢出) 87 #define set_T1M CKCON |= SET_BIT4 //设置定时器1的时钟为系统时钟(0为1/12系统时钟,与8051兼容，1为选择时钟源为系统时钟) 88 #define set_T0M CKCON |= SET_BIT3 //设置定时器0的时钟为系统时钟(0为1/12系统时钟,与8051兼容，1为选择时钟源为系统时钟) 89 #define set_CLOEN CKCON |= SET_BIT1 //设置系统时钟输出使能,从PLO(P1.1)输出(0禁用系统时钟输出,1使系统时钟创覲LO(P1.1)输出) 90 //清除时钟 91 #define clr_PWMCKS CKCON &= ~SET_BIT6 //设置pwm时钟源为系统时钟(0为系统时钟，1为定时器1的溢出) 92 #define clr_T1M CKCON &= ~SET_BIT4 //设置定时器1的时钟为1/12系统时钟(0为1/12系统时钟,与8051兼容，1为选择时钟源为系统时钟) 93 #define clr_T0M CKCON &= ~SET_BIT3 //设置定时器0的时钟为1/12系统时钟(0为1/12系统时钟,与8051兼容，1为选择时钟源为系统时钟) 94 #define clr_CLOEN CKCON &= ~SET_BIT1 //设置系统时钟输出使能,禁用系统时钟输出(0禁用系统时钟输出,1使系统时钟创覲LO(P1.1)输出) 95 96 //**** WKCON 8FH **** 97 #define set_WKTCK WKCON |= SET_BIT5 98 #define set_WKTF WKCON |= SET_BIT4 99 #define set_WKTR WKCON |= SET_BIT3 100 #define set_WKPS2 WKCON |= SET_BIT2 101 #define set_WKPS1 WKCON |= SET_BIT1 102 #define set_WKPS0 WKCON |= SET_BIT0 103 104 #define clr_WKTCK WKCON &= ~SET_BIT5 105 #define clr_WKTF WKCON &= ~SET_BIT4 106 #define clr_WKTR WKCON &= ~SET_BIT3 107 #define clr_WKPS2 WKCON &= ~SET_BIT2 108 #define clr_WKPS1 WKCON &= ~SET_BIT1 109 #define clr_WKPS0 WKCON &= ~SET_BIT0 110 111 /**** P1 90H *****/ 112 #define set_P10 P10 = 1 113 #define set_P11 P11 = 1 114 #define set_P12 P12 = 1 115 #define set_P13 P13 = 1 116 #define set_P14 P14 = 1 117 #define set_P15 P15 = 1 118 #define set_P16 P16 = 1 119 #define set_P17 P17 = 1 120 121 #define clr_P10 P10 = 0 122 #define clr_P11 P11 = 0 123 #define clr_P12 P12 = 0 124 #define clr_P13 P13 = 0 125 #define clr_P14 P14 = 0 126 #define clr_P15 P15 = 0 127 #define clr_P16 P16 = 0 128 #define clr_P17 P17 = 0 129 130 //****SFRS 91H **** 131 #define set_SFRPAGE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=SET_BIT0;EA=BIT_TMP 132 #define clr_SFRPAGE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS&=~SET_BIT0;EA=BIT_TMP 133 134 //****CAPCON0 92H **** 135 #define set_CAPEN2 CAPCON0 |= SET_BIT6 136 #define set_CAPEN1 CAPCON0 |= SET_BIT5 137 #define set_CAPEN0 CAPCON0 |= SET_BIT4 138 #define set_CAPF2 CAPCON0 |= SET_BIT2 139 #define set_CAPF1 CAPCON0 |= SET_BIT1 140 #define set_CAPF0 CAPCON0 |= SET_BIT0 141 142 #define clr_CAPEN2 CAPCON0 &= ~SET_BIT6 143 #define clr_CAPEN1 CAPCON0 &= ~SET_BIT5 144 #define clr_CAPEN0 CAPCON0 &= ~SET_BIT4 145 #define clr_CAPF2 CAPCON0 &= ~SET_BIT2 146 #define clr_CAPF1 CAPCON0 &= ~SET_BIT1 147 #define clr_CAPF0 CAPCON0 &= ~SET_BIT0 148 149 //**** CAPCON1 93H **** 150 #define set_CAP2LS1 CAPCON1 |= SET_BIT5 151 #define set_CAP2LS0 CAPCON1 |= SET_BIT4 152 #define set_CAP1LS1 CAPCON1 |= SET_BIT3 153 #define set_CAP1LS0 CAPCON1 |= SET_BIT2 154 #define set_CAP0LS1 CAPCON1 |= SET_BIT1 155 #define set_CAP0LS0 CAPCON1 |= SET_BIT0 156 157 #define clr_CAP2LS1 CAPCON1 &= ~SET_BIT5 158 #define clr_CAP2LS0 CAPCON1 &= ~SET_BIT4 159 #define clr_CAP1LS1 CAPCON1 &= ~SET_BIT3 160 #define clr_CAP1LS0 CAPCON1 &= ~SET_BIT2 161 #define clr_CAP0LS1 CAPCON1 &= ~SET_BIT1 162 #define clr_CAP0LS0 CAPCON1 &= ~SET_BIT0 163 164 //**** CAPCON2 94H **** 165 #define set_ENF2 CAPCON2 |= SET_BIT6 166 #define set_ENF1 CAPCON2 |= SET_BIT5 167 #define set_ENF0 CAPCON2 |= SET_BIT4 168 169 #define clr_ENF2 CAPCON2 &= ~SET_BIT6 170 #define clr_ENF1 CAPCON2 &= ~SET_BIT5 171 #define clr_ENF0 CAPCON2 &= ~SET_BIT4 172 173 //**** CKDIV 95H **** 174 175 //**** CKSWT 96H **** TA protect register 176 #define set_HIRCST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT5;EA=BIT_TMP; 177 #define set_LIRCST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT4;EA=BIT_TMP; 178 #define set_ECLKST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT3;EA=BIT_TMP; 179 #define set_OSC1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT2;EA=BIT_TMP; 180 #define set_OSC0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT|=SET_BIT1;EA=BIT_TMP; 181 182 #define clr_HIRCST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT5;EA=BIT_TMP; 183 #define clr_LIRCST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT4;EA=BIT_TMP; 184 #define clr_ECLKST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT3;EA=BIT_TMP; 185 #define clr_OSC1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT2;EA=BIT_TMP; 186 #define clr_OSC0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKSWT&=~SET_BIT1;EA=BIT_TMP; 187 188 //**** CKEN 97H **** TA protect register 189 #define set_EXTEN1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN|=SET_BIT7;EA=BIT_TMP; 190 #define set_EXTEN0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN|=SET_BIT6;EA=BIT_TMP; 191 #define set_HIRCEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN|=SET_BIT5;EA=BIT_TMP; 192 #define set_CKSWTF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN|=SET_BIT0;EA=BIT_TMP; 193 194 #define clr_EXTEN1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN&=~SET_BIT7;EA=BIT_TMP; 195 #define clr_EXTEN0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN&=~SET_BIT6;EA=BIT_TMP; 196 #define clr_HIRCEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN&=~SET_BIT5;EA=BIT_TMP; 197 #define clr_CKSWTF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CKEN&=~SET_BIT0;EA=BIT_TMP; 198 199 //**** SCON 98H **** 200 #define set_FE FE = 1 201 #define set_SM1 SM1 = 1 202 #define set_SM2 SM2 = 1 203 #define set_REN REN = 1 204 #define set_TB8 TB8 = 1 205 #define set_RB8 RB8 = 1 206 #define set_TI TI = 1 207 #define set_RI RI = 1 208 209 #define clr_FE FE = 0 210 #define clr_SM1 SM1 = 0 211 #define clr_SM2 SM2 = 0 212 #define clr_REN REN = 0 213 #define clr_TB8 TB8 = 0 214 #define clr_RB8 RB8 = 0 215 #define clr_TI TI = 0 216 #define clr_RI RI = 0 217 218 //**** SBUF 99H **** 219 //**** SBUF_1 9AH **** 220 221 //**** EIE 9BH **** 222 #define set_ET2 EIE |= SET_BIT7 223 #define set_ESPI EIE |= SET_BIT6 224 #define set_EFB EIE |= SET_BIT5 225 #define set_EWDT EIE |= SET_BIT4 226 #define set_EPWM EIE |= SET_BIT3 227 #define set_ECAP EIE |= SET_BIT2 228 #define set_EPI EIE |= SET_BIT1 229 #define set_EI2C EIE |= SET_BIT0 230 231 #define clr_ET2 EIE &= ~SET_BIT7 232 #define clr_ESPI EIE &= ~SET_BIT6 233 #define clr_EFB EIE &= ~SET_BIT5 234 #define clr_EWDT EIE &= ~SET_BIT4 235 #define clr_EPWM EIE &= ~SET_BIT3 236 #define clr_ECAP EIE &= ~SET_BIT2 237 #define clr_EPI EIE &= ~SET_BIT1 238 #define clr_EI2C EIE &= ~SET_BIT0 239 240 //**** EIE1 9CH **** 241 #define set_EWKT EIE1 |= SET_BIT2 242 #define set_ET3 EIE1 |= SET_BIT1 243 #define set_ES_1 EIE1 |= SET_BIT0 244 245 #define clr_EWKT EIE1 &= ~SET_BIT2 246 #define clr_ET3 EIE1 &= ~SET_BIT1 247 #define clr_ES_1 EIE1 &= ~SET_BIT0 248 249 //**** CHPCON 9DH **** TA protect register 250 #define set_SWRST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON|=SET_BIT7 ;EA=BIT_TMP 251 #define set_IAPFF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON|=SET_BIT6 ;EA=BIT_TMP 252 #define set_BS BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON|=SET_BIT1 ;EA=BIT_TMP 253 #define set_IAPEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON|=SET_BIT0 ;EA=BIT_TMP 254 255 #define clr_SWRST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON&=~SET_BIT7;EA=BIT_TMP 256 #define clr_IAPFF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON&=~SET_BIT6;EA=BIT_TMP 257 #define clr_BS BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON&=~SET_BIT1;EA=BIT_TMP 258 #define clr_IAPEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;CHPCON&=~SET_BIT0;EA=BIT_TMP 259 260 //**** P2 A0H **** 261 262 //**** AUXR1 A2H **** 263 #define set_SWRF AUXR1 |= SET_BIT7 264 #define set_RSTPINF AUXR1 |= SET_BIT6 265 #define set_HARDF AUXR1 |= SET_BIT5 266 #define set_GF2 AUXR1 |= SET_BIT3 267 #define set_UART0PX AUXR1 |= SET_BIT2 268 #define set_DPS AUXR1 |= SET_BIT0 269 270 #define clr_SWRF AUXR1 &= ~SET_BIT7 271 #define clr_RSTPINF AUXR1 &= ~SET_BIT6 272 #define clr_HARDF AUXR1 &= ~SET_BIT5 273 #define clr_GF2 AUXR1 &= ~SET_BIT3 274 #define clr_UART0PX AUXR1 &= ~SET_BIT2 275 #define clr_DPS AUXR1 &= ~SET_BIT0 276 277 //**** BODCON0 A3H **** TA protect register 278 #define set_BODEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT7;EA=BIT_TMP 279 #define set_BOV2 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT6;EA=BIT_TMP 280 #define set_BOV1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT5;EA=BIT_TMP 281 #define set_BOV0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT4;EA=BIT_TMP 282 #define set_BOF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT3;EA=BIT_TMP 283 #define set_BORST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT2;EA=BIT_TMP 284 #define set_BORF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT1;EA=BIT_TMP 285 #define set_BOS BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0|=SET_BIT0;EA=BIT_TMP 286 287 #define clr_BODEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT7;EA=BIT_TMP 288 #define clr_BOV2 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT6;EA=BIT_TMP 289 #define clr_BOV1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT5;EA=BIT_TMP 290 #define clr_BOV0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT4;EA=BIT_TMP 291 #define clr_BOF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT3;EA=BIT_TMP 292 #define clr_BORST BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT2;EA=BIT_TMP 293 #define clr_BORF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT1;EA=BIT_TMP 294 #define clr_BOS BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON0&=~SET_BIT0;EA=BIT_TMP 295 296 //**** IAPTRG A4H **** TA protect register 297 #define set_IAPGO BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPTRG|=SET_BIT0 ;EA=BIT_TMP 298 #define clr_IAPGO BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPTRG&=~SET_BIT0;EA=BIT_TMP 299 300 //**** IAPUEN A5H **** TA protect register 301 #define set_CFUEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN|=SET_BIT2;EA=BIT_TMP 302 #define set_LDUEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN|=SET_BIT1;EA=BIT_TMP 303 #define set_APUEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN|=SET_BIT0;EA=BIT_TMP 304 305 #define clr_CFUEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN&=~SET_BIT2;EA=BIT_TMP 306 #define clr_LDUEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN&=~SET_BIT1;EA=BIT_TMP 307 #define clr_APUEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;IAPUEN&=~SET_BIT0;EA=BIT_TMP 308 309 //**** IAPAL A6H **** 310 //**** IAPAH A7H **** 311 312 //IE A8H 中断时能寄存器 313 #define set_EA EA = 1 //使能开启所有中断(0禁止所有中断，1每个中断使能依靠使能单独中断将会产生相应的单个中断) 314 #define set_EADC EADC = 1 //使能开启ADC中断(0禁止ADC中断,1使能由ADCF(ADCCON0.7)产生中断) 315 #define set_EBOD EBOD = 1 //使能开启BOD中段(0禁止BOD中断,1使能有BOD(BODCON0.3)产生中断) 316 #define set_ES ES = 1 //使能开启串口0中断(0禁止串口0中断,1使能由T1(SCON.1)或RI(SCON.0)中断) 317 #define set_ET1 ET1 = 1 318 #define set_EX1 EX1 = 1 319 #define set_ET0 ET0 = 1 //使能定时器0中断(0禁止定时器0中断,1使能由TF0(TCON.5)产生中断) 320 #define set_EX0 EX0 = 1 321 322 #define clr_EA EA = 0 323 #define clr_EADC EADC = 0 324 #define clr_EBOD EBOD = 0 325 #define clr_ES ES = 0 326 #define clr_ET1 ET1 = 0 327 #define clr_EX1 EX1 = 0 328 #define clr_ET0 ET0 = 0 329 #define clr_EX0 EX0 = 0 330 331 //**** SADDR A9H **** 332 333 //**** WDCON AAH **** TA protect register 334 #define set_WDTR BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT7;EA=BIT_TMP; 335 #define set_WDCLR BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT6;EA=BIT_TMP; 336 #define set_WDTF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT5;EA=BIT_TMP; 337 #define set_WIDPD BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT4;EA=BIT_TMP; 338 #define set_WDTRF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT3;EA=BIT_TMP; 339 #define set_WPS2 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT2;EA=BIT_TMP; 340 #define set_WPS1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT1;EA=BIT_TMP; 341 #define set_WPS0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON|=SET_BIT0;EA=BIT_TMP; 342 343 #define clr_WDTEN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT7;EA=BIT_TMP; 344 #define clr_WDCLR BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT6;EA=BIT_TMP; 345 #define clr_WDTF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT5;EA=BIT_TMP; 346 #define clr_WDTRF BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT3;EA=BIT_TMP; 347 #define clr_WPS2 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT2;EA=BIT_TMP; 348 #define clr_WPS1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT1;EA=BIT_TMP; 349 #define clr_WPS0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;WDCON&=~SET_BIT0;EA=BIT_TMP; 350 351 //**** BODCON1 ABH **** TA protect register 352 #define set_LPBOD1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1|=SET_BIT2 ;EA=BIT_TMP; 353 #define set_LPBOD0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1|=SET_BIT1 ;EA=BIT_TMP; 354 #define set_BODFLT BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1|=SET_BIT0 ;EA=BIT_TMP; 355 356 #define clr_LPBOD1 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1&=~SET_BIT2;EA=BIT_TMP; 357 #define clr_LPBOD0 BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1&=~SET_BIT1;EA=BIT_TMP; 358 #define clr_BODFLT BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;BODCON1&=~SET_BIT0;EA=BIT_TMP; 359 360 361 //**** P3M1 ACH PAGE0 **** 362 #define set_P3M1_0 P3M1 |= SET_BIT0 363 #define clr_P3M1_0 P3M1 &= ~SET_BIT0 364 365 //**** P3S ACH PAGE1 **** SFRS must set as 1 to modify this register 366 #define set_P3S_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P3S|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 367 #define clr_P3S_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P3S&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 368 369 //**** P3M2 ADH PAGE0 **** 370 #define set_P3M2_0 P3M2 |= SET_BIT0 371 #define clr_P3M2_0 P3M2 &= ~SET_BIT0 372 373 //**** P3SR ADH PAGE1 **** SFRS must set as 1 to modify this register 374 #define set_P3SR_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P3SR|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 375 #define clr_P3SR_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P3SR&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 376 377 //**** IAPFD AEH **** 378 379 //**** IAPCN AFH **** 380 #define set_FOEN IAPN |= SET_BIT5 381 #define set_FCEN IAPN |= SET_BIT4 382 #define set_FCTRL3 IAPN |= SET_BIT3 383 #define set_FCTRL2 IAPN |= SET_BIT2 384 #define set_FCTRL1 IAPN |= SET_BIT1 385 #define set_FCTRL0 IAPN |= SET_BIT0 386 387 #define clr_FOEN IAPN &= ~SET_BIT5 388 #define clr_FCEN IAPN &= ~SET_BIT4 389 #define clr_FCTRL3 IAPN &= ~SET_BIT3 390 #define clr_FCTRL2 IAPN &= ~SET_BIT2 391 #define clr_FCTRL1 IAPN &= ~SET_BIT1 392 #define clr_FCTRL0 IAPN &= ~SET_BIT0 393 394 //**** P3 B0H **** 395 #define set_P30 P30 = 1 396 #define clr_P30 P30 = 0 397 398 //**** P0M1 B1H PAGE0 **** 399 #define set_P0M1_7 P0M1 |= SET_BIT7 400 #define set_P0M1_6 P0M1 |= SET_BIT6 401 #define set_P0M1_5 P0M1 |= SET_BIT5 402 #define set_P0M1_4 P0M1 |= SET_BIT4 403 #define set_P0M1_3 P0M1 |= SET_BIT3 404 #define set_P0M1_2 P0M1 |= SET_BIT2 405 #define set_P0M1_1 P0M1 |= SET_BIT1 406 #define set_P0M1_0 P0M1 |= SET_BIT0 407 408 #define clr_P0M1_7 P0M1 &= ~SET_BIT7 409 #define clr_P0M1_6 P0M1 &= ~SET_BIT6 410 #define clr_P0M1_5 P0M1 &= ~SET_BIT5 411 #define clr_P0M1_4 P0M1 &= ~SET_BIT4 412 #define clr_P0M1_3 P0M1 &= ~SET_BIT3 413 #define clr_P0M1_2 P0M1 &= ~SET_BIT2 414 #define clr_P0M1_1 P0M1 &= ~SET_BIT1 415 #define clr_P0M1_0 P0M1 &= ~SET_BIT0 416 417 //**** P0S B2H PAGE1 **** SFRS must set as 1 to modify this register 418 #define set_P0S_7 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 419 #define set_P0S_6 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 420 #define set_P0S_5 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 421 #define set_P0S_4 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 422 #define set_P0S_3 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 423 #define set_P0S_2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 424 #define set_P0S_1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 425 #define set_P0S_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 426 427 #define clr_P0S_7 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 428 #define clr_P0S_6 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 429 #define clr_P0S_5 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 430 #define clr_P0S_4 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 431 #define clr_P0S_3 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 432 #define clr_P0S_2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 433 #define clr_P0S_1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 434 #define clr_P0S_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0S&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 435 436 //**** P0M2 B2H PAGE0 **** 437 #define set_P0M2_7 P0M2 |= SET_BIT7 438 #define set_P0M2_6 P0M2 |= SET_BIT6 439 #define set_P0M2_5 P0M2 |= SET_BIT5 440 #define set_P0M2_4 P0M2 |= SET_BIT4 441 #define set_P0M2_3 P0M2 |= SET_BIT3 442 #define set_P0M2_2 P0M2 |= SET_BIT2 443 #define set_P0M2_1 P0M2 |= SET_BIT1 444 #define set_P0M2_0 P0M2 |= SET_BIT0 445 446 #define clr_P0M2_7 P0M2 &= ~SET_BIT7 447 #define clr_P0M2_6 P0M2 &= ~SET_BIT6 448 #define clr_P0M2_5 P0M2 &= ~SET_BIT5 449 #define clr_P0M2_4 P0M2 &= ~SET_BIT4 450 #define clr_P0M2_3 P0M2 &= ~SET_BIT3 451 #define clr_P0M2_2 P0M2 &= ~SET_BIT2 452 #define clr_P0M2_1 P0M2 &= ~SET_BIT1 453 #define clr_P0M2_0 P0M2 &= ~SET_BIT0 454 455 456 //**** P0SR B0H PAGE1 **** SFRS must set as 1 to modify this register 457 #define set_P0SR_7 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 458 #define set_P0SR_6 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 459 #define set_P0SR_5 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 460 #define set_P0SR_4 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 461 #define set_P0SR_3 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 462 #define set_P0SR_2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 463 #define set_P0SR_1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 464 #define set_P0SR_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 465 466 #define clr_P0SR_7 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 467 #define clr_P0SR_6 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 468 #define clr_P0SR_5 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 469 #define clr_P0SR_4 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 470 #define clr_P0SR_3 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 471 #define clr_P0SR_2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 472 #define clr_P0SR_1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 473 #define clr_P0SR_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P0SR&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 474 475 476 //**** P1M1 B3H PAGE0 **** 477 #define set_P1M1_7 P1M1 |= SET_BIT7 478 #define set_P1M1_6 P1M1 |= SET_BIT6 479 #define set_P1M1_5 P1M1 |= SET_BIT5 480 #define set_P1M1_4 P1M1 |= SET_BIT4 481 #define set_P1M1_3 P1M1 |= SET_BIT3 482 #define set_P1M1_2 P1M1 |= SET_BIT2 483 #define set_P1M1_1 P1M1 |= SET_BIT1 484 #define set_P1M1_0 P1M1 |= SET_BIT0 485 486 #define clr_P1M1_7 P1M1 &= ~SET_BIT7 487 #define clr_P1M1_6 P1M1 &= ~SET_BIT6 488 #define clr_P1M1_5 P1M1 &= ~SET_BIT5 489 #define clr_P1M1_4 P1M1 &= ~SET_BIT4 490 #define clr_P1M1_3 P1M1 &= ~SET_BIT3 491 #define clr_P1M1_2 P1M1 &= ~SET_BIT2 492 #define clr_P1M1_1 P1M1 &= ~SET_BIT1 493 #define clr_P1M1_0 P1M1 &= ~SET_BIT0 494 495 //**** P1S B3H PAGE1 **** SFRS must set as 1 to modify this register 496 #define set_P1S_7 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 497 #define set_P1S_6 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 498 #define set_P1S_5 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 499 #define set_P1S_4 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 500 #define set_P1S_3 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 501 #define set_P1S_2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 502 #define set_P1S_1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 503 #define set_P1S_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 504 505 #define clr_P1S_7 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 506 #define clr_P1S_6 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 507 #define clr_P1S_5 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 508 #define clr_P1S_4 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 509 #define clr_P1S_3 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 510 #define clr_P1S_2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 511 #define clr_P1S_1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 512 #define clr_P1S_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1S&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 513 514 //**** P1M2 B4H PAGE0 **** 515 #define set_P12UP P1M2 |= SET_BIT2 516 #define set_P1M2_1 P1M2 |= SET_BIT1 517 #define set_P1M2_0 P1M2 |= SET_BIT0 518 519 #define clr_P12UP P1M2 &= ~SET_BIT2 520 #define clr_P1M2_1 P1M2 &= ~SET_BIT1 521 #define clr_P1M2_0 P1M2 &= ~SET_BIT0 522 523 //**** P1SR B4H PAGE1 **** SFRS must set as 1 to modify this register 524 #define set_P1SR_7 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 525 #define set_P1SR_6 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 526 #define set_P1SR_5 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 527 #define set_P1SR_4 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 528 #define set_P1SR_3 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 529 #define set_P1SR_2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 530 #define set_P1SR_1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 531 #define set_P1SR_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 532 533 #define clr_P1SR_7 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT7;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 534 #define clr_P1SR_6 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT6;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 535 #define clr_P1SR_5 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 536 #define clr_P1SR_4 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 537 #define clr_P1SR_3 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 538 #define clr_P1SR_2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 539 #define clr_P1SR_1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 540 #define clr_P1SR_0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;P1SR&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 541 542 543 //**** P2S B5H **** 544 #define set_P2S_0 P2S |= SET_BIT0 545 #define clr_P2S_0 P2S &= ~SET_BIT0 546 547 //**** IPH B7H PAGE0 **** 548 #define set_PADCH IPH |= SET_BIT6 549 #define set_PBODH IPH |= SET_BIT5 550 #define set_PSH IPH |= SET_BIT4 551 #define set_PT1H IPH |= SET_BIT3 552 #define set_PX11 IPH |= SET_BIT2 553 #define set_PT0H IPH |= SET_BIT1 554 #define set_PX0H IPH |= SET_BIT0 555 556 #define clr_PADCH IPH &= ~SET_BIT6 557 #define clr_PBODH IPH &= ~SET_BIT5 558 #define clr_PSH IPH &= ~SET_BIT4 559 #define clr_PT1H IPH &= ~SET_BIT3 560 #define clr_PX11 IPH &= ~SET_BIT2 561 #define clr_PT0H IPH &= ~SET_BIT1 562 #define clr_PX0H IPH &= ~SET_BIT0 563 564 //**** PWMINTC B7H PAGE1 **** SFRS must set as 1 to modify this register 565 #define set_INTTYP1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 566 #define set_INTTYP0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 567 #define set_INTSEL2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 568 #define set_INTSEL1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 569 #define set_INTSEL0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 570 571 #define clr_INTTYP1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 572 #define clr_INTTYP0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT4;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 573 #define clr_INTSEL2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 574 #define clr_INTSEL1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 575 #define clr_INTSEL0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 576 577 //**** IP B8H **** 578 #define set_PADC PADC = 1 579 #define set_PBOD PBOD = 1 580 #define set_PS PS = 1 581 #define set_PT1 PT1 = 1 582 #define set_PX1 PX1 = 1 583 #define set_PT0 PT0 = 1 584 #define set_PX0 PX0 = 1 585 586 #define clr_PADC PADC = 0 587 #define clr_PBOD PBOD = 0 588 #define clr_PS PS = 0 589 #define clr_PT1 PT1 = 0 590 #define clr_PX1 PX1 = 0 591 #define clr_PT0 PT0 = 0 592 #define clr_PX0 PX0 = 0 593 594 //**** SADEN B9H **** 595 //**** SADEN_1 8AH **** 596 //**** SADDR_1 BBH **** 597 //**** I2DAT BCH **** 598 //**** I2STAT BDH **** 599 //**** I2CLK BEH **** 600 601 //**** I2TOC BFH **** 602 #define set_I2TOCEN I2TOC |= SET_BIT2 603 #define set_DIV I2TOC |= SET_BIT1 604 #define set_I2TOF I2TOC |= SET_BIT0 605 606 #define clr_I2TOCEN I2TOC &= ~SET_BIT2 607 #define clr_DIV I2TOC &= ~SET_BIT1 608 #define clr_I2TOF I2TOC &= ~SET_BIT0 609 610 //**** I2CON C0H **** 611 #define set_I2CEN I2CEN = 1 612 #define set_STA STA = 1 613 #define set_STO STO = 1 614 #define set_SI SI = 1 615 #define set_AA AA = 1 616 #define set_I2CPX I2CPX = 1 617 618 #define clr_I2CEN I2CEN = 0 619 #define clr_STA STA = 0 620 #define clr_STO STO = 0 621 #define clr_SI SI = 0 622 #define clr_AA AA = 0 623 #define clr_I2CPX I2CPX = 0 624 625 //**** I2ADDR C1H **** 626 #define set_GC I2ADDR |= SET_BIT0 627 #define clr_GC I2ADDR &= ~SET_BIT0 628 629 //**** ADCRL C2H **** 630 //**** ADCRH C3H **** 631 632 //**** T3CON C4H PAGE0 **** 633 #define set_SMOD_1 T3CON |= SET_BIT7 634 #define set_SMOD0_1 T3CON |= SET_BIT6 635 #define set_BRCK T3CON |= SET_BIT5 636 #define set_TF3 T3CON |= SET_BIT4 637 #define set_TR3 T3CON |= SET_BIT3 638 #define set_T3PS2 T3CON |= SET_BIT2 639 #define set_T3PS1 T3CON |= SET_BIT1 640 #define set_T3PS0 T3CON |= SET_BIT0 641 642 #define clr_SMOD_1 T3CON &= ~SET_BIT7 643 #define clr_SMOD0_1 T3CON &= ~SET_BIT6 644 #define clr_BRCK T3CON &= ~SET_BIT5 645 #define clr_TF3 T3CON &= ~SET_BIT4 646 #define clr_TR3 T3CON &= ~SET_BIT3 647 #define clr_T3PS2 T3CON &= ~SET_BIT2 648 #define clr_T3PS1 T3CON &= ~SET_BIT1 649 #define clr_T3PS0 T3CON &= ~SET_BIT0 650 651 //**** PWM4H C4H PAGE1 **** SFRS must set as 1 to modify this register 652 //**** RL3 C5H PAGE0 **** 653 //**** PWM5H C5H PAGE1 **** SFRS must set as 1 to modify this register 654 //**** RH3 C6H PAGE0 **** 655 656 //**** PIOCON1 C6H PAGE1 **** SFRS must set as 1 to modify this register 657 #define set_PIO15 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1|=SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 658 #define set_PIO13 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1|=SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 659 #define set_PIO12 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1|=SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 660 #define set_PIO11 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 661 662 #define clr_PIO15 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1&=~SET_BIT5;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 663 #define clr_PIO13 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1&=~SET_BIT3;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 664 #define clr_PIO12 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1&=~SET_BIT2;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 665 #define clr_PIO11 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PIOCON1&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 666 667 //**** T2CON C8H **** 668 #define set_TF2 TF2 = 1 669 #define set_TR2 TR2 = 1 670 #define set_CMRL2 CMRL2 = 1 671 672 #define clr_TF2 TF2 = 0 673 #define clr_TR2 TR2 = 0 674 #define clr_CMRL2 CMRL2 = 0 675 676 //**** T2MOD C9H **** 677 #define set_LDEN T2MOD |= SET_BIT7 678 #define set_T2DIV2 T2MOD |= SET_BIT6 679 #define set_T2DIV1 T2MOD |= SET_BIT5 680 #define set_T2DIV0 T2MOD |= SET_BIT4 681 #define set_CAPCR T2MOD |= SET_BIT3 682 #define set_CMPCR T2MOD |= SET_BIT2 683 #define set_LDTS1 T2MOD |= SET_BIT1 684 #define set_LDTS0 T2MOD |= SET_BIT0 685 686 #define clr_LDEN T2MOD &= ~SET_BIT7 687 #define clr_T2DIV2 T2MOD &= ~SET_BIT6 688 #define clr_T2DIV1 T2MOD &= ~SET_BIT5 689 #define clr_T2DIV0 T2MOD &= ~SET_BIT4 690 #define clr_CAPCR T2MOD &= ~SET_BIT3 691 #define clr_CMPCR T2MOD &= ~SET_BIT2 692 #define clr_LDTS1 T2MOD &= ~SET_BIT1 693 #define clr_LDTS0 T2MOD &= ~SET_BIT0 694 695 //**** RCMP2H CAH **** 696 //**** RCMP2L CBH **** 697 //**** TL2 CCH PAGE0 **** 698 //**** PWM4L CCH PAGE1 **** SFRS must set as 1 to modify this register 699 //**** TH2 CDH PAGE0 **** 700 //**** PWM5L CDH PAGE1 **** SFRS must set as 1 to modify this register 701 //**** ADCMPL CEH **** 702 //**** ADCMPH CFH **** 703 704 /**** PSW D0H ****/ 705 #define set_CY CY = 1 706 #define set_AC AC = 1 707 #define set_F0 F0 = 1 708 #define set_RS1 RS1 = 1 709 #define set_RS0 RS0 = 1 710 #define set_OV OV = 1 711 #define set_P P = 1 712 713 #define clr_CY CY = 0 714 #define clr_AC AC = 0 715 #define clr_F0 F0 = 0 716 #define clr_RS1 RS1 = 0 717 #define clr_RS0 RS0 = 0 718 #define clr_OV OV = 0 719 #define clr_P P = 0 720 721 //**** PWMPH D1H **** 722 //**** PWM0H D2H **** 723 //**** PWM1H D3H **** 724 //**** PWM2H D4H **** 725 //**** PWM3H D5H **** 726 727 //**** PNP D6H **** 728 #define set_PNP5 PNP |= SET_BIT5 729 #define set_PNP4 PNP |= SET_BIT4 730 #define set_PNP3 PNP |= SET_BIT3 731 #define set_PNP2 PNP |= SET_BIT2 732 #define set_PNP1 PNP |= SET_BIT1 733 #define set_PNP0 PNP |= SET_BIT0 734 735 #define clr_PNP5 PNP &= ~SET_BIT5 736 #define clr_PNP4 PNP &= ~SET_BIT4 737 #define clr_PNP3 PNP &= ~SET_BIT3 738 #define clr_PNP2 PNP &= ~SET_BIT2 739 #define clr_PNP1 PNP &= ~SET_BIT1 740 #define clr_PNP0 PNP &= ~SET_BIT0 741 742 //**** FBD D7H **** 743 #define set_FBF FBD |= SET_BIT7 744 #define set_FBINLS FBD |= SET_BIT6 745 #define set_FBD5 FBD |= SET_BIT5 746 #define set_FBD4 FBD |= SET_BIT4 747 #define set_FBD3 FBD |= SET_BIT3 748 #define set_FBD2 FBD |= SET_BIT2 749 #define set_FBD1 FBD |= SET_BIT1 750 #define set_FBD0 FBD |= SET_BIT0 751 752 #define clr_FBF FBD &= ~SET_BIT7 753 #define clr_FBINLS FBD &= ~SET_BIT6 754 #define clr_FBD5 FBD &= ~SET_BIT5 755 #define clr_FBD4 FBD &= ~SET_BIT4 756 #define clr_FBD3 FBD &= ~SET_BIT3 757 #define clr_FBD2 FBD &= ~SET_BIT2 758 #define clr_FBD1 FBD &= ~SET_BIT1 759 #define clr_FBD0 FBD &= ~SET_BIT0 760 761 /**** PWMCON0 D8H ****/ 762 #define set_PWMRUN PWMRUN = 1 //运行PWM使能 763 #define set_LOAD LOAD = 1 //写：更新PWM值(本次结束更新)，读：（导入新的pwm没有完成） 764 #define set_PWMF PWMF = 1 // 765 #define set_CLRPWM CLRPWM = 1 //写：清空pwm寄存器，读：PWM 16位计数器内还有数值，未清零 766 767 #define clr_PWMRUN PWMRUN = 0 //关闭PWM使能 768 #define clr_LOAD LOAD = 0 //写：=导入新周期和占空比已经完成，读：=当前一个PWM周期输出结束，载入动作才会开始 769 #define clr_PWMF PWMF = 0 // 770 #define clr_CLRPWM CLRPWM = 0 //写： 无动作，读： PWM 16位计数器已清零 771 772 //**** PWMPL D9H **** 773 //**** PWM0L DAH **** 774 //**** PWM1L DBH **** 775 //**** PWM2L DCH **** 776 //**** PWM3L DDH **** 777 778 //**** PIOCON0 DEH **** 779 #define set_PIO05 PIOCON0 |= SET_BIT5 780 #define set_PIO04 PIOCON0 |= SET_BIT4 781 #define set_PIO03 PIOCON0 |= SET_BIT3 782 #define set_PIO02 PIOCON0 |= SET_BIT2 783 #define set_PIO01 PIOCON0 |= SET_BIT1 784 #define set_PIO00 PIOCON0 |= SET_BIT0 785 786 #define clr_PIO05 PIOCON0 &= ~SET_BIT5 787 #define clr_PIO04 PIOCON0 &= ~SET_BIT4 788 #define clr_PIO03 PIOCON0 &= ~SET_BIT3 789 #define clr_PIO02 PIOCON0 &= ~SET_BIT2 790 #define clr_PIO01 PIOCON0 &= ~SET_BIT1 791 #define clr_PIO00 PIOCON0 &= ~SET_BIT0 792 793 //**** PWMCON1 DFH **** 794 #define set_PWMMOD1 PWMCON1 |= SET_BIT7 795 #define set_PWMMOD0 PWMCON1 |= SET_BIT6 796 #define set_GP PWMCON1 |= SET_BIT5 797 #define set_PWMTYP PWMCON1 |= SET_BIT4 798 #define set_FBINEN PWMCON1 |= SET_BIT3 799 #define set_PWMDIV2 PWMCON1 |= SET_BIT2 800 #define set_PWMDIV1 PWMCON1 |= SET_BIT1 801 #define set_PWMDIV0 PWMCON1 |= SET_BIT0 802 803 #define clr_PWMMOD1 PWMCON1 &= ~SET_BIT7 804 #define clr_PWMMOD0 PWMCON1 &= ~SET_BIT6 805 #define clr_GP PWMCON1 &= ~SET_BIT5 806 #define clr_PWMTYP PWMCON1 &= ~SET_BIT4 807 #define clr_FBINEN PWMCON1 &= ~SET_BIT3 808 #define clr_PWMDIV2 PWMCON1 &= ~SET_BIT2 809 #define clr_PWMDIV1 PWMCON1 &= ~SET_BIT1 810 #define clr_PWMDIV0 PWMCON1 &= ~SET_BIT0 811 812 //**** ACC E0H **** 813 814 //**** ADCCON1 E1H **** 815 #define set_STADCPX ADCCON1 |= SET_BIT6 816 #define set_ETGTYP1 ADCCON1 |= SET_BIT3 817 #define set_ETGTYP0 ADCCON1 |= SET_BIT2 818 #define set_ADCEX ADCCON1 |= SET_BIT1 819 #define set_ADCEN ADCCON1 |= SET_BIT0 820 821 #define clr_STADCPX ADCCON1 &= ~SET_BIT6 822 #define clr_ETGTYP1 ADCCON1 &= ~SET_BIT3 823 #define clr_ETGTYP0 ADCCON1 &= ~SET_BIT2 824 #define clr_ADCEX ADCCON1 &= ~SET_BIT1 825 #define clr_ADCEN ADCCON1 &= ~SET_BIT0 826 827 //**** ADCON2 E2H **** 828 #define set_ADFBEN ADCCON2 |= SET_BIT7 829 #define set_ADCMPOP ADCCON2 |= SET_BIT6 830 #define set_ADCMPEN ADCCON2 |= SET_BIT5 831 #define set_ADCMPO ADCCON2 |= SET_BIT4 832 833 #define clr_ADFBEN ADCCON2 &= ~SET_BIT7 834 #define clr_ADCMPOP ADCCON2 &= ~SET_BIT6 835 #define clr_ADCMPEN ADCCON2 &= ~SET_BIT5 836 #define clr_ADCMPO ADCCON2 &= ~SET_BIT4 837 838 //**** ADCDLY E3H **** 839 //**** C0L E4H **** 840 //**** C0H E5H **** 841 //**** C1L E6H **** 842 //**** C1H E7H **** 843 844 //**** ADCCON0 EAH **** 845 #define set_ADCF ADCF = 1 846 #define set_ADCS ADCS = 1 847 #define set_ETGSEL1 ETGSEL1 = 1 848 #define set_ETGSEL0 ETGSEL0 = 1 849 #define set_ADCHS3 ADCHS3 = 1 850 #define set_ADCHS2 ADCHS2 = 1 851 #define set_ADCHS1 ADCHS1 = 1 852 #define set_ADCHS0 ADCHS0 = 1 853 854 #define clr_ADCF ADCF = 0 855 #define clr_ADCS ADCS = 0 856 #define clr_ETGSEL1 ETGSEL1 = 0 857 #define clr_ETGSEL0 ETGSEL0 = 0 858 #define clr_ADCHS3 ADCHS3 = 0 859 #define clr_ADCHS2 ADCHS2 = 0 860 #define clr_ADCHS1 ADCHS1 = 0 861 #define clr_ADCHS0 ADCHS0 = 0 862 863 //**** PICON E9H **** 864 #define set_PIT67 PICON |= SET_BIT7 865 #define set_PIT45 PICON |= SET_BIT6 866 #define set_PIT3 PICON |= SET_BIT5 867 #define set_PIT2 PICON |= SET_BIT4 868 #define set_PIT1 PICON |= SET_BIT3 869 #define set_PIT0 PICON |= SET_BIT2 870 #define set_PIPS1 PICON |= SET_BIT1 871 #define set_PIPS0 PICON |= SET_BIT0 872 873 #define clr_PIT67 PICON &= ~SET_BIT7 874 #define clr_PIT45 PICON &= ~SET_BIT6 875 #define clr_PIT3 PICON &= ~SET_BIT5 876 #define clr_PIT2 PICON &= ~SET_BIT4 877 #define clr_PIT1 PICON &= ~SET_BIT3 878 #define clr_PIT0 PICON &= ~SET_BIT2 879 #define clr_PIPS1 PICON &= ~SET_BIT1 880 #define clr_PIPS0 PICON &= ~SET_BIT0 881 882 //**** PINEN EAH **** 883 #define set_PINEN7 PINEN |= SET_BIT7 884 #define set_PINEN6 PINEN |= SET_BIT6 885 #define set_PINEN5 PINEN |= SET_BIT5 886 #define set_PINEN4 PINEN |= SET_BIT4 887 #define set_PINEN3 PINEN |= SET_BIT3 888 #define set_PINEN2 PINEN |= SET_BIT2 889 #define set_PINEN1 PINEN |= SET_BIT1 890 #define set_PINEN0 PINEN |= SET_BIT0 891 892 #define clr_PINEN7 PINEN &= ~SET_BIT7 893 #define clr_PINEN6 PINEN &= ~SET_BIT6 894 #define clr_PINEN5 PINEN &= ~SET_BIT5 895 #define clr_PINEN4 PINEN &= ~SET_BIT4 896 #define clr_PINEN3 PINEN &= ~SET_BIT3 897 #define clr_PINEN2 PINEN &= ~SET_BIT2 898 #define clr_PINEN1 PINEN &= ~SET_BIT1 899 #define clr_PINEN0 PINEN &= ~SET_BIT0 900 901 //**** PIPEN EBH **** 902 #define set_PIPEN7 PIPEN |= SET_BIT7 903 #define set_PIPEN6 PIPEN |= SET_BIT6 904 #define set_PIPEN5 PIPEN |= SET_BIT5 905 #define set_PIPEN4 PIPEN |= SET_BIT4 906 #define set_PIPEN3 PIPEN |= SET_BIT3 907 #define set_PIPEN2 PIPEN |= SET_BIT2 908 #define set_PIPEN1 PIPEN |= SET_BIT1 909 #define set_PIPEN0 PIPEN |= SET_BIT0 910 911 #define clr_PIPEN7 PIPEN &= ~SET_BIT7 912 #define clr_PIPEN6 PIPEN &= ~SET_BIT6 913 #define clr_PIPEN5 PIPEN &= ~SET_BIT5 914 #define clr_PIPEN4 PIPEN &= ~SET_BIT4 915 #define clr_PIPEN3 PIPEN &= ~SET_BIT3 916 #define clr_PIPEN2 PIPEN &= ~SET_BIT2 917 #define clr_PIPEN1 PIPEN &= ~SET_BIT1 918 #define clr_PIPEN0 PIPEN &= ~SET_BIT0 919 920 //**** PIF ECH **** 921 #define set_PIF7 PIF |= SET_BIT7 922 #define set_PIF6 PIF |= SET_BIT6 923 #define set_PIF5 PIF |= SET_BIT5 924 #define set_PIF4 PIF |= SET_BIT4 925 #define set_PIF3 PIF |= SET_BIT3 926 #define set_PIF2 PIF |= SET_BIT2 927 #define set_PIF1 PIF |= SET_BIT1 928 #define set_PIF0 PIF |= SET_BIT0 929 930 #define clr_PIF7 PIF &= ~SET_BIT7 931 #define clr_PIF6 PIF &= ~SET_BIT6 932 #define clr_PIF5 PIF &= ~SET_BIT5 933 #define clr_PIF4 PIF &= ~SET_BIT4 934 #define clr_PIF3 PIF &= ~SET_BIT3 935 #define clr_PIF2 PIF &= ~SET_BIT2 936 #define clr_PIF1 PIF &= ~SET_BIT1 937 #define clr_PIF0 PIF &= ~SET_BIT0 938 939 //**** C2L EDH **** 940 //**** C2H EEH **** 941 942 //**** EIP EFH **** 943 #define set_PT2 EIP |= SET_BIT7 944 #define set_PSPI EIP |= SET_BIT6 945 #define set_PFB EIP |= SET_BIT5 946 #define set_PWDT EIP |= SET_BIT4 947 #define set_PPWM EIP |= SET_BIT3 948 #define set_PCAP EIP |= SET_BIT2 949 #define set_PPI EIP |= SET_BIT1 950 #define set_PI2C EIP |= SET_BIT0 951 952 #define clr_PT2 EIP &= ~SET_BIT7 953 #define clr_PSPI EIP &= ~SET_BIT6 954 #define clr_PFB EIP &= ~SET_BIT5 955 #define clr_PWDT EIP &= ~SET_BIT4 956 #define clr_PPWM EIP &= ~SET_BIT3 957 #define clr_PCAP EIP &= ~SET_BIT2 958 #define clr_PPI EIP &= ~SET_BIT1 959 #define clr_PI2C EIP &= ~SET_BIT0 960 961 //**** B F0H **** 962 963 //**** CAPCON3 F1H **** 964 #define set_CAP13 CAPCON3 |= SET_BIT7 965 #define set_CAP12 CAPCON3 |= SET_BIT6 966 #define set_CAP11 CAPCON3 |= SET_BIT5 967 #define set_CAP10 CAPCON3 |= SET_BIT4 968 #define set_CAP03 CAPCON3 |= SET_BIT3 969 #define set_CAP02 CAPCON3 |= SET_BIT2 970 #define set_CAP01 CAPCON3 |= SET_BIT1 971 #define set_CAP00 CAPCON3 |= SET_BIT0 972 973 #define clr_CAP13 CAPCON3 &= ~SET_BIT7 974 #define clr_CAP12 CAPCON3 &= ~SET_BIT6 975 #define clr_CAP11 CAPCON3 &= ~SET_BIT5 976 #define clr_CAP10 CAPCON3 &= ~SET_BIT4 977 #define clr_CAP03 CAPCON3 &= ~SET_BIT3 978 #define clr_CAP02 CAPCON3 &= ~SET_BIT2 979 #define clr_CAP01 CAPCON3 &= ~SET_BIT1 980 #define clr_CAP00 CAPCON3 &= ~SET_BIT0 981 982 //**** CAPCON4 F2H **** 983 #define set_CAP23 CAPCON4 |= SET_BIT3 984 #define set_CAP22 CAPCON4 |= SET_BIT2 985 #define set_CAP21 CAPCON4 |= SET_BIT1 986 #define set_CAP20 CAPCON4 |= SET_BIT0 987 988 #define clr_CAP23 CAPCON4 &= ~SET_BIT3 989 #define clr_CAP22 CAPCON4 &= ~SET_BIT2 990 #define clr_CAP21 CAPCON4 &= ~SET_BIT1 991 #define clr_CAP20 CAPCON4 &= ~SET_BIT0 992 993 //**** SPCR F3H PAGE0 **** 994 #define set_SSOE SPCR |= SET_BIT7 995 #define set_SPIEN SPCR |= SET_BIT6 996 #define set_LSBFE SPCR |= SET_BIT5 997 #define set_MSTR SPCR |= SET_BIT4 998 #define set_CPOL SPCR |= SET_BIT3 999 #define set_CPHA SPCR |= SET_BIT2 1000 #define set_SPR1 SPCR |= SET_BIT1 1001 #define set_SPR0 SPCR |= SET_BIT0 1002 1003 #define clr_SSOE SPCR &= ~SET_BIT7 1004 #define clr_SPIEN SPCR &= ~SET_BIT6 1005 #define clr_LSBFE SPCR &= ~SET_BIT5 1006 #define clr_MSTR SPCR &= ~SET_BIT4 1007 #define clr_CPOL SPCR &= ~SET_BIT3 1008 #define clr_CPHA SPCR &= ~SET_BIT2 1009 #define clr_SPR1 SPCR &= ~SET_BIT1 1010 #define clr_SPR0 SPCR &= ~SET_BIT0 1011 1012 //**** SPCR2 F3H PAGE1 **** SFRS must set as 1 to modify this register 1013 #define set_SPIS1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;SPCR2|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 1014 #define set_SPIS0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x00;SPCR2|=SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 1015 1016 #define clr_SPIS1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x00;SPCR2&=~SET_BIT1;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 1017 #define clr_SPIS0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x00;SPCR2&=~SET_BIT0;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 1018 1019 //**** SPSR F4H **** 1020 #define set_SPIF SPSR |= SET_BIT7 1021 #define set_WCOL SPSR |= SET_BIT6 1022 #define set_SPIOVF SPSR |= SET_BIT5 1023 #define set_MODF SPSR |= SET_BIT4 1024 #define set_DISMODF SPSR |= SET_BIT3 1025 1026 #define clr_SPIF SPSR &= ~SET_BIT7 1027 #define clr_WCOL SPSR &= ~SET_BIT6 1028 #define clr_SPIOVF SPSR &= ~SET_BIT5 1029 #define clr_MODF SPSR &= ~SET_BIT4 1030 #define clr_DISMODF SPSR &= ~SET_BIT3 1031 1032 //**** SPDR F5H **** 1033 1034 //**** AINDIDS F6H **** 1035 #define set_P11DIDS AINDIDS |= SET_BIT7 1036 #define set_P03DIDS AINDIDS |= SET_BIT6 1037 #define set_P04DIDS AINDIDS |= SET_BIT5 1038 #define set_P05DIDS AINDIDS |= SET_BIT4 1039 #define set_P06DIDS AINDIDS |= SET_BIT3 1040 #define set_P07DIDS AINDIDS |= SET_BIT2 1041 #define set_P30DIDS AINDIDS |= SET_BIT1 1042 #define set_P17DIDS AINDIDS |= SET_BIT0 1043 1044 #define clr_P11DIDS AINDIDS &= ~SET_BIT7 1045 #define clr_P03DIDS AINDIDS &= ~SET_BIT6 1046 #define clr_P04DIDS AINDIDS &= ~SET_BIT5 1047 #define clr_P05DIDS AINDIDS &= ~SET_BIT4 1048 #define clr_P06DIDS AINDIDS &= ~SET_BIT3 1049 #define clr_P07DIDS AINDIDS &= ~SET_BIT2 1050 #define clr_P30DIDS AINDIDS &= ~SET_BIT1 1051 #define clr_P17DIDS AINDIDS &= ~SET_BIT0 1052 1053 //**** EIPH F7H **** 1054 #define set_PT2H EIPH |= SET_BIT7 1055 #define set_PSPIH EIPH |= SET_BIT6 1056 #define set_PFBH EIPH |= SET_BIT5 1057 #define set_PWDTH EIPH |= SET_BIT4 1058 #define set_PPWMH EIPH |= SET_BIT3 1059 #define set_PCAPH EIPH |= SET_BIT2 1060 #define set_PPIH EIPH |= SET_BIT1 1061 #define set_PI2CH EIPH |= SET_BIT0 1062 1063 #define clr_PT2H EIPH &= ~SET_BIT7 1064 #define clr_PSPIH EIPH &= ~SET_BIT6 1065 #define clr_PFBH EIPH &= ~SET_BIT5 1066 #define clr_PWDTH EIPH &= ~SET_BIT4 1067 #define clr_PPWMH EIPH &= ~SET_BIT3 1068 #define clr_PCAPH EIPH &= ~SET_BIT2 1069 #define clr_PPIH EIPH &= ~SET_BIT1 1070 #define clr_PI2CH EIPH &= ~SET_BIT0 1071 1072 /**** SCON_1 F8H ****/ 1073 #define set_FE_1 FE_1 = 1 1074 #define set_SM1_1 SM1_1 = 1 1075 #define set_SM2_1 SM2_1 = 1 1076 #define set_REN_1 REN_1 = 1 1077 #define set_TB8_1 TB8_1 = 1 1078 #define set_RB8_1 RB8_1 = 1 1079 #define set_TI_1 TI_1 = 1 1080 #define set_RI_1 RI_1 = 1 1081 1082 #define clr_FE_1 FE_1 = 0 1083 #define clr_SM1_1 SM1_1 = 0 1084 #define clr_SM2_1 SM2_1 = 0 1085 #define clr_REN_1 REN_1 = 0 1086 #define clr_TB8_1 TB8_1 = 0 1087 #define clr_RB8_1 RB8_1 = 0 1088 #define clr_TI_1 TI_1 = 0 1089 #define clr_RI_1 RI_1 = 0 1090 1091 //**** PDTEN F9H **** 1092 #define set_PDT45EN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|= SET_BIT2 ;EA=BIT_TMP; 1093 #define set_PDT23EN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|= SET_BIT1 ;EA=BIT_TMP; 1094 #define set_PDT01EN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|= SET_BIT0 ;EA=BIT_TMP; 1095 1096 #define clr_PDT45EN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN &= ~SET_BIT2 ;EA=BIT_TMP; 1097 #define clr_PDT23EN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN &= ~SET_BIT1 ;EA=BIT_TMP; 1098 #define clr_PDT01EN BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN &= ~SET_BIT0 ;EA=BIT_TMP; 1099 1100 //**** PDTCNT FAH **** 1101 1102 //**** PMEN FBH **** 1103 #define set_PMEN5 PMEN |= SET_BIT5 1104 #define set_PMEN4 PMEN |= SET_BIT4 1105 #define set_PMEN3 PMEN |= SET_BIT3 1106 #define set_PMEN2 PMEN |= SET_BIT2 1107 #define set_PMEN1 PMEN |= SET_BIT1 1108 #define set_PMEN0 PMEN |= SET_BIT0 1109 1110 #define clr_PMEN5 PMEN &= ~SET_BIT5 1111 #define clr_PMEN4 PMEN &= ~SET_BIT4 1112 #define clr_PMEN3 PMEN &= ~SET_BIT3 1113 #define clr_PMEN2 PMEN &= ~SET_BIT2 1114 #define clr_PMEN1 PMEN &= ~SET_BIT1 1115 #define clr_PMEN0 PMEN &= ~SET_BIT0 1116 1117 //**** PMD FCH **** 1118 #define set_PMD7 PMD |= SET_BIT7 1119 #define set_PMD6 PMD |= SET_BIT6 1120 #define set_PMD5 PMD |= SET_BIT5 1121 #define set_PMD4 PMD |= SET_BIT4 1122 #define set_PMD3 PMD |= SET_BIT3 1123 #define set_PMD2 PMD |= SET_BIT2 1124 #define set_PMD1 PMD |= SET_BIT1 1125 #define set_PMD0 PMD |= SET_BIT0 1126 1127 #define clr_PMD7 PMD &= ~SET_BIT7 1128 #define clr_PMD6 PMD &= ~SET_BIT6 1129 #define clr_PMD5 PMD &= ~SET_BIT5 1130 #define clr_PMD4 PMD &= ~SET_BIT4 1131 #define clr_PMD3 PMD &= ~SET_BIT3 1132 #define clr_PMD2 PMD &= ~SET_BIT2 1133 #define clr_PMD1 PMD &= ~SET_BIT1 1134 #define clr_PMD0 PMD &= ~SET_BIT0 1135 1136 //**** EIP1 FEH **** 1137 #define set_PWKT EIP1 |= SET_BIT2 1138 #define set_PT3 EIP1 |= SET_BIT1 1139 #define set_PS_1 EIP1 |= SET_BIT0 1140 1141 #define clr_PWKT EIP1 &= ~SET_BIT2 1142 #define clr_PT3 EIP1 &= ~SET_BIT1 1143 #define clr_PS_1 EIP1 &= ~SET_BIT0 1144 1145 //**** EIPH1 FFH **** 1146 #define set_PWKTH EIPH1 |= SET_BIT2 1147 #define set_PT3H EIPH1 |= SET_BIT1 1148 #define set_PSH_1 EIPH1 |= SET_BIT0 1149 1150 #define clr_PWKTH EIPH1 &= ~SET_BIT2 1151 #define clr_PT3H EIPH1 &= ~SET_BIT1 1152 #define clr_PSH_1 EIPH1 &= ~SET_BIT0
1 /*-------------------------------------------------------------------------- 2 N76E003 Function_define.h V1.02 3 4 All function define inital setting file for Nuvoton N76E003 5 --------------------------------------------------------------------------*/ 6 7 #include <intrins.h> 8 #include <stdio.h> 9 10 #define nop _nop_(); 11 12 13 //16 --> 8 x 2 14 #define HIBYTE(v1) ((UINT8)((v1)>>8)) //v1 is UINT16 15 #define LOBYTE(v1) ((UINT8)((v1)&0xFF)) 16 //8 x 2 --> 16 17 #define MAKEWORD(v1,v2) ((((UINT16)(v1))<<8)+(UINT16)(v2)) //v1,v2 is UINT8 18 //8 x 4 --> 32 19 #define MAKELONG(v1,v2,v3,v4) (UINT32)((v1<<24)+(v2<<16)+(v3<<8)+v4) //v1,v2,v3,v4 is UINT8 20 //32 --> 16 x 2 21 #define YBYTE1(v1) ((UINT16)((v1)>>16)) //v1 is UINT32 22 #define YBYTE0(v1) ((UINT16)((v1)&0xFFFF)) 23 //32 --> 8 x 4 24 #define TBYTE3(v1) ((UINT8)((v1)>>24)) //v1 is UINT32 25 #define TBYTE2(v1) ((UINT8)((v1)>>16)) 26 #define TBYTE1(v1) ((UINT8)((v1)>>8)) 27 #define TBYTE0(v1) ((UINT8)((v1)&0xFF)) 28 29 #define SET_BIT0 0x01 30 #define SET_BIT1 0x02 31 #define SET_BIT2 0x04 32 #define SET_BIT3 0x08 33 #define SET_BIT4 0x10 34 #define SET_BIT5 0x20 35 #define SET_BIT6 0x40 36 #define SET_BIT7 0x80 37 #define SET_BIT8 0x0100 38 #define SET_BIT9 0x0200 39 #define SET_BIT10 0x0400 40 #define SET_BIT11 0x0800 41 #define SET_BIT12 0x1000 42 #define SET_BIT13 0x2000 43 #define SET_BIT14 0x4000 44 #define SET_BIT15 0x8000 45 46 #define CLR_BIT0 0xFE 47 #define CLR_BIT1 0xFD 48 #define CLR_BIT2 0xFB 49 #define CLR_BIT3 0xF7 50 #define CLR_BIT4 0xEF 51 #define CLR_BIT5 0xDF 52 #define CLR_BIT6 0xBF 53 #define CLR_BIT7 0x7F 54 55 #define CLR_BIT8 0xFEFF 56 #define CLR_BIT9 0xFDFF 57 #define CLR_BIT10 0xFBFF 58 #define CLR_BIT11 0xF7FF 59 #define CLR_BIT12 0xEFFF 60 #define CLR_BIT13 0xDFFF 61 #define CLR_BIT14 0xBFFF 62 #define CLR_BIT15 0x7FFF 63 64 #define FAIL 1 65 #define PASS 0 66 67 /***************************************************************************************** 68 * For GPIO INIT setting 69 *****************************************************************************************/ 70 //------------------- Define Port as Quasi mode ------------------- 71 #define P00_Quasi_Mode P0M1&=~SET_BIT0;P0M2&=~SET_BIT0 72 #define P01_Quasi_Mode P0M1&=~SET_BIT1;P0M2&=~SET_BIT1 73 #define P02_Quasi_Mode P0M1&=~SET_BIT2;P0M2&=~SET_BIT2 74 #define P03_Quasi_Mode P0M1&=~SET_BIT3;P0M2&=~SET_BIT3 75 #define P04_Quasi_Mode P0M1&=~SET_BIT4;P0M2&=~SET_BIT4 76 #define P05_Quasi_Mode P0M1&=~SET_BIT5;P0M2&=~SET_BIT5 77 #define P06_Quasi_Mode P0M1&=~SET_BIT6;P0M2&=~SET_BIT6 78 #define P07_Quasi_Mode P0M1&=~SET_BIT7;P0M2&=~SET_BIT7 79 #define P10_Quasi_Mode P1M1&=~SET_BIT0;P1M2&=~SET_BIT0 80 #define P11_Quasi_Mode P1M1&=~SET_BIT1;P1M2&=~SET_BIT1 81 #define P12_Quasi_Mode P1M1&=~SET_BIT2;P1M2&=~SET_BIT2 82 #define P13_Quasi_Mode P1M1&=~SET_BIT3;P1M2&=~SET_BIT3 83 #define P14_Quasi_Mode P1M1&=~SET_BIT4;P1M2&=~SET_BIT4 84 #define P15_Quasi_Mode P1M1&=~SET_BIT5;P1M2&=~SET_BIT5 85 #define P16_Quasi_Mode P1M1&=~SET_BIT6;P1M2&=~SET_BIT6 86 #define P17_Quasi_Mode P1M1&=~SET_BIT7;P1M2&=~SET_BIT7 87 #define P30_Quasi_Mode P3M1&=~SET_BIT0;P3M2&=~SET_BIT0 88 //------------------- Define Port as Push Pull mode ------------------- 89 #define P00_PushPull_Mode P0M1&=~SET_BIT0;P0M2|=SET_BIT0 90 #define P01_PushPull_Mode P0M1&=~SET_BIT1;P0M2|=SET_BIT1 91 #define P02_PushPull_Mode P0M1&=~SET_BIT2;P0M2|=SET_BIT2 92 #define P03_PushPull_Mode P0M1&=~SET_BIT3;P0M2|=SET_BIT3 93 #define P04_PushPull_Mode P0M1&=~SET_BIT4;P0M2|=SET_BIT4 94 #define P05_PushPull_Mode P0M1&=~SET_BIT5;P0M2|=SET_BIT5 95 #define P06_PushPull_Mode P0M1&=~SET_BIT6;P0M2|=SET_BIT6 96 #define P07_PushPull_Mode P0M1&=~SET_BIT7;P0M2|=SET_BIT7 97 #define P10_PushPull_Mode P1M1&=~SET_BIT0;P1M2|=SET_BIT0 98 #define P11_PushPull_Mode P1M1&=~SET_BIT1;P1M2|=SET_BIT1 99 #define P12_PushPull_Mode P1M1&=~SET_BIT2;P1M2|=SET_BIT2 100 #define P13_PushPull_Mode P1M1&=~SET_BIT3;P1M2|=SET_BIT3 101 #define P14_PushPull_Mode P1M1&=~SET_BIT4;P1M2|=SET_BIT4 102 #define P15_PushPull_Mode P1M1&=~SET_BIT5;P1M2|=SET_BIT5 103 #define P16_PushPull_Mode P1M1&=~SET_BIT6;P1M2|=SET_BIT6 104 #define P17_PushPull_Mode P1M1&=~SET_BIT7;P1M2|=SET_BIT7 105 #define P30_PushPull_Mode P3M1&=~SET_BIT0;P3M2|=SET_BIT0 106 #define GPIO1_PushPull_Mode P1M1&=~SET_BIT0;P1M2|=SET_BIT0 107 //------------------- Define Port as Input Only mode ------------------- 108 #define P00_Input_Mode P0M1|=SET_BIT0;P0M2&=~SET_BIT0 109 #define P01_Input_Mode P0M1|=SET_BIT1;P0M2&=~SET_BIT1 110 #define P02_Input_Mode P0M1|=SET_BIT2;P0M2&=~SET_BIT2 111 #define P03_Input_Mode P0M1|=SET_BIT3;P0M2&=~SET_BIT3 112 #define P04_Input_Mode P0M1|=SET_BIT4;P0M2&=~SET_BIT4 113 #define P05_Input_Mode P0M1|=SET_BIT5;P0M2&=~SET_BIT5 114 #define P06_Input_Mode P0M1|=SET_BIT6;P0M2&=~SET_BIT6 115 #define P07_Input_Mode P0M1|=SET_BIT7;P0M2&=~SET_BIT7 116 #define P10_Input_Mode P1M1|=SET_BIT0;P1M2&=~SET_BIT0 117 #define P11_Input_Mode P1M1|=SET_BIT1;P1M2&=~SET_BIT1 118 #define P12_Input_Mode P1M1|=SET_BIT2;P1M2&=~SET_BIT2 119 #define P13_Input_Mode P1M1|=SET_BIT3;P1M2&=~SET_BIT3 120 #define P14_Input_Mode P1M1|=SET_BIT4;P1M2&=~SET_BIT4 121 #define P15_Input_Mode P1M1|=SET_BIT5;P1M2&=~SET_BIT5 122 #define P16_Input_Mode P1M1|=SET_BIT6;P1M2&=~SET_BIT6 123 #define P17_Input_Mode P1M1|=SET_BIT7;P1M2&=~SET_BIT7 124 #define P30_Input_Mode P3M1|=SET_BIT0;P3M2&=~SET_BIT0 125 //-------------------Define Port as Open Drain mode ------------------- 126 #define P00_OpenDrain_Mode P0M1|=SET_BIT0;P0M2|=SET_BIT0 127 #define P01_OpenDrain_Mode P0M1|=SET_BIT1;P0M2|=SET_BIT1 128 #define P02_OpenDrain_Mode P0M1|=SET_BIT2;P0M2|=SET_BIT2 129 #define P03_OpenDrain_Mode P0M1|=SET_BIT3;P0M2|=SET_BIT3 130 #define P04_OpenDrain_Mode P0M1|=SET_BIT4;P0M2|=SET_BIT4 131 #define P05_OpenDrain_Mode P0M1|=SET_BIT5;P0M2|=SET_BIT5 132 #define P06_OpenDrain_Mode P0M1|=SET_BIT6;P0M2|=SET_BIT6 133 #define P07_OpenDrain_Mode P0M1|=SET_BIT7;P0M2|=SET_BIT7 134 #define P10_OpenDrain_Mode P1M1|=SET_BIT0;P1M2|=SET_BIT0 135 #define P11_OpenDrain_Mode P1M1|=SET_BIT1;P1M2|=SET_BIT1 136 #define P12_OpenDrain_Mode P1M1|=SET_BIT2;P1M2|=SET_BIT2 137 #define P13_OpenDrain_Mode P1M1|=SET_BIT3;P1M2|=SET_BIT3 138 #define P14_OpenDrain_Mode P1M1|=SET_BIT4;P1M2|=SET_BIT4 139 #define P15_OpenDrain_Mode P1M1|=SET_BIT5;P1M2|=SET_BIT5 140 #define P16_OpenDrain_Mode P1M1|=SET_BIT6;P1M2|=SET_BIT6 141 #define P17_OpenDrain_Mode P1M1|=SET_BIT7;P1M2|=SET_BIT7 142 #define P30_OpenDrain_Mode P3M1|=SET_BIT0;P3M2|=SET_BIT0 143 //--------- Define all port as quasi mode --------- 144 #define Set_All_GPIO_Quasi_Mode P0M1=0;P0M2=0;P1M1=0;P1M2=0;P3M1=0;P3M2=0 145 146 #define set_GPIO1 P12=1 147 #define clr_GPIO1 P12=0 148 static bit BIT_TMP; 149 /**************************************************************************** 150 Enable INT port 0~3 151 ***************************************************************************/ 152 #define Enable_INT_Port0 PICON &= 0xFB; 153 #define Enable_INT_Port1 PICON |= 0x01; 154 #define Enable_INT_Port2 PICON |= 0x02; 155 #define Enable_INT_Port3 PICON |= 0x03; 156 /***************************************************************************** 157 Enable each bit low level trig mode 158 *****************************************************************************/ 159 #define Enable_BIT7_LowLevel_Trig PICON&=0x7F;PINEN|=0x80;PIPEN&=0x7F 160 #define Enable_BIT6_LowLevel_Trig PICON&=0x7F;PINEN|=0x40;PIPEN&=0xBF 161 #define Enable_BIT5_LowLevel_Trig PICON&=0xBF;PINEN|=0x20;PIPEN&=0xDF 162 #define Enable_BIT4_LowLevel_Trig PICON&=0xBF;PINEN|=0x10;PIPEN&=0xEF 163 #define Enable_BIT3_LowLevel_Trig PICON&=0xDF;PINEN|=0x08;PIPEN&=0xF7 164 #define Enable_BIT2_LowLevel_Trig PICON&=0xEF;PINEN|=0x04;PIPEN&=0xFB 165 #define Enable_BIT1_LowLevel_Trig PICON&=0xF7;PINEN|=0x02;PIPEN&=0xFD 166 #define Enable_BIT0_LowLevel_Trig PICON&=0xFD;PINEN|=0x01;PIPEN&=0xFE 167 /***************************************************************************** 168 Enable each bit high level trig mode 169 *****************************************************************************/ 170 #define Enable_BIT7_HighLevel_Trig PICON&=0x7F;PINEN&=0x7F;PIPEN|=0x80 171 #define Enable_BIT6_HighLevel_Trig PICON&=0x7F;PINEN&=0xBF;PIPEN|=0x40 172 #define Enable_BIT5_HighLevel_Trig PICON&=0xBF;PINEN&=0xDF;PIPEN|=0x20 173 #define Enable_BIT4_HighLevel_Trig PICON&=0xBF;PINEN&=0xEF;PIPEN|=0x10 174 #define Enable_BIT3_HighLevel_Trig PICON&=0xDF;PINEN&=0xF7;PIPEN|=0x08 175 #define Enable_BIT2_HighLevel_Trig PICON&=0xEF;PINEN&=0xFB;PIPEN|=0x04 176 #define Enable_BIT1_HighLevel_Trig PICON&=0xF7;PINEN&=0xFD;PIPEN|=0x02 177 #define Enable_BIT0_HighLevel_Trig PICON&=0xFD;PINEN&=0xFE;PIPEN|=0x01 178 /***************************************************************************** 179 Enable each bit falling edge trig mode 180 *****************************************************************************/ 181 #define Enable_BIT7_FallEdge_Trig PICON|=0x80;PINEN|=0x80;PIPEN&=0x7F 182 #define Enable_BIT6_FallEdge_Trig PICON|=0x80;PINEN|=0x40;PIPEN&=0xBF 183 #define Enable_BIT5_FallEdge_Trig PICON|=0x40;PINEN|=0x20;PIPEN&=0xDF 184 #define Enable_BIT4_FallEdge_Trig PICON|=0x40;PINEN|=0x10;PIPEN&=0xEF 185 #define Enable_BIT3_FallEdge_Trig PICON|=0x20;PINEN|=0x08;PIPEN&=0xF7 186 #define Enable_BIT2_FallEdge_Trig PICON|=0x10;PINEN|=0x04;PIPEN&=0xFB 187 #define Enable_BIT1_FallEdge_Trig PICON|=0x08;PINEN|=0x02;PIPEN&=0xFD 188 #define Enable_BIT0_FallEdge_Trig PICON|=0x04;PINEN|=0x01;PIPEN&=0xFE 189 /***************************************************************************** 190 Enable each bit rasing edge trig mode 191 *****************************************************************************/ 192 #define Enable_BIT7_RasingEdge_Trig PICON|=0x80;PINEN&=0x7F;PIPEN|=0x80 193 #define Enable_BIT6_RasingEdge_Trig PICON|=0x80;PINEN&=0xBF;PIPEN|=0x40 194 #define Enable_BIT5_RasingEdge_Trig PICON|=0x40;PINEN&=0xDF;PIPEN|=0x20 195 #define Enable_BIT4_RasingEdge_Trig PICON|=0x40;PINEN&=0xEF;PIPEN|=0x10 196 #define Enable_BIT3_RasingEdge_Trig PICON|=0x20;PINEN&=0xF7;PIPEN|=0x08 197 #define Enable_BIT2_RasingEdge_Trig PICON|=0x10;PINEN&=0xFB;PIPEN|=0x04 198 #define Enable_BIT1_RasingEdge_Trig PICON|=0x08;PINEN|=0xFD;PIPEN&=0x02 199 #define Enable_BIT0_RasingEdge_Trig PICON|=0x04;PINEN|=0xFE;PIPEN&=0x01 200 201 202 /***************************************************************************************** 203 * For TIMER VALUE setting is base on " option -> C51 -> Preprocesser Symbols -> Define " 204 *****************************************************************************************/ 205 #ifdef FOSC_110592 // if Fsys = 11.0592MHz 206 #define TIMER_DIV12_VALUE_10us 65536-9 //9*12/11.0592 = 10 uS, // Timer divider = 12 for TM0/TM1 207 #define TIMER_DIV12_VALUE_1ms 65536-923 //923*12/11.0592 = 1 mS // Timer divider = 12 208 #define TIMER_DIV12_VALUE_10ms 65536-9216 //18432*12/22118400 = 10 ms // Timer divider = 12 209 #define TIMER_DIV4_VALUE_10us 65536-28 //28*4/11.0592 = 10 uS // Timer divider = 4 for TM2/TM3 210 #define TIMER_DIV4_VALUE_1ms 65536-2765 //2765*4/11.0592 = 1 mS // Timer divider = 4 211 #define TIMER_DIV4_VALUE_100us 65536-277 //553*4/22118400 = 100 us // Timer divider = 4 212 #define TIMER_DIV4_VALUE_200us 65536-553 //1106*4/22118400 = 200 us // Timer divider = 4 213 #define TIMER_DIV4_VALUE_500us 65536-1383 //2765*4/22118400 = 500 us // Timer divider = 4 214 #define TIMER_DIV16_VALUE_10ms 65536-6912 //1500*16/22118400 = 10 ms // Timer divider = 16 215 #define TIMER_DIV64_VALUE_30ms 65536-5184 //10368*64/22118400 = 30 ms // Timer divider = 64 216 #define TIMER_DIV128_VALUE_100ms 65536-8640 //17280*128/22118400 = 100 ms // Timer divider = 128 217 #define TIMER_DIV128_VALUE_200ms 65536-17280 //34560*128/22118400 = 200 ms // Timer divider = 128 218 #define TIMER_DIV256_VALUE_500ms 65536-21600 //43200*256/22118400 = 500 ms // Timer divider = 256 219 #define TIMER_DIV512_VALUE_1s 65536-21600 //43200*512/22118400 = 1 s // Timer divider = 512 220 #endif 221 #ifdef FOSC_160000 // if Fsys = 16MHz 222 #define TIMER_DIV12_VALUE_10us 65536-13 //13*12/16000000 = 10 uS, // Timer divider = 12 for TM0/TM1 223 #define TIMER_DIV12_VALUE_100us 65536-130 //130*12/16000000 = 10 uS, // Timer divider = 12 224 #define TIMER_DIV12_VALUE_1ms 65536-1334 //1334*12/16000000 = 1 mS, // Timer divider = 12 225 #define TIMER_DIV12_VALUE_10ms 65536-13334 //13334*12/16000000 = 10 mS // Timer divider = 12 226 #define TIMER_DIV12_VALUE_40ms 65536-53336 //53336*12/16000000 = 40 ms // Timer divider = 12 227 #define TIMER_DIV4_VALUE_10us 65536-40 //40*4/16000000 = 10 uS, // Timer divider = 4 for TM2/TM3 228 #define TIMER_DIV4_VALUE_100us 65536-400 //400*4/16000000 = 100 us // Timer divider = 4 229 #define TIMER_DIV4_VALUE_200us 65536-800 //800*4/16000000 = 200 us // Timer divider = 4 230 #define TIMER_DIV4_VALUE_500us 65536-2000 //2000*4/16000000 = 500 us // Timer divider = 4 231 #define TIMER_DIV4_VALUE_1ms 65536-4000 //4000*4/16000000 = 1 mS, // Timer divider = 4 232 #define TIMER_DIV16_VALUE_10ms 65536-10000 //10000*16/16000000 = 10 ms // Timer divider = 16 233 #define TIMER_DIV64_VALUE_30ms 65536-7500 //7500*64/16000000 = 30 ms // Timer divider = 64 234 #define TIMER_DIV128_VALUE_100ms 65536-12500 //12500*128/16000000 = 100 ms // Timer divider = 128 235 #define TIMER_DIV128_VALUE_200ms 65536-25000 //25000*128/16000000 = 200 ms // Timer divider = 128 236 #define TIMER_DIV256_VALUE_500ms 65536-31250 //31250*256/16000000 = 500 ms // Timer divider = 256 237 #define TIMER_DIV512_VALUE_1s 65536-31250 //31250*512/16000000 = 1 s. // Timer Divider = 512 238 #endif 239 #ifdef FOSC_184320 // if Fsys = 18.432MHz 240 #define TIMER_DIV12_VALUE_10us 65536-15 //15*12/18.432 = 10 uS, Timer Clock = Fsys/12 241 #define TIMER_DIV12_VALUE_1ms 65536-1536 //1536*12/18.432 = 1 mS, Timer Clock = Fsys/12 242 #define TIMER_DIV4_VALUE_10us 65536-46 //46*4/18.432 = 10 uS, Timer Clock = Fsys/4 243 #define TIMER_DIV4_VALUE_1ms 65536-4608 //4608*4/18.432 = 1 mS, Timer Clock = Fsys/4 244 #endif 245 #ifdef FOSC_200000 // if Fsys = 20 MHz 246 #define TIMER_DIV12_VALUE_10us 65536-17 //17*12/20000000 = 10 uS, Timer Clock = Fsys/12 247 #define TIMER_DIV12_VALUE_1ms 65536-1667 //1667*12/20000000 = 1 mS, Timer Clock = Fsys/12 248 #define TIMER_DIV4_VALUE_10us 65536-50 //50*4/20000000 = 10 uS, Timer Clock = Fsys/4 249 #define TIMER_DIV4_VALUE_1ms 65536-5000 //5000*4/20000000 = 1 mS, Timer Clock = Fsys/4 250 #endif 251 #ifdef FOSC_221184 // if Fsys = 22.1184 MHz 252 #define TIMER_DIV12_VALUE_10us 65536-18 //18*12/22118400 = 10 uS, // Timer divider = 12 253 #define TIMER_DIV12_VALUE_1ms 65536-1843 //1843*12/22118400 = 1 mS, // Timer divider = 12 254 #define TIMER_DIV12_VALUE_10ms 65536-18432 //18432*12/22118400 = 10 ms // Timer divider = 12 255 #define TIMER_DIV4_VALUE_10us 65536-56 //9*4/22118400 = 10 uS, // Timer divider = 4 256 #define TIMER_DIV4_VALUE_1ms 65536-5530 //923*4/22118400 = 1 mS, // Timer divider = 4 257 #define TIMER_DIV4_VALUE_100us 65536-553 //553*4/22118400 = 100 us // Timer divider = 4 258 #define TIMER_DIV4_VALUE_200us 65536-1106 //1106*4/22118400 = 200 us // Timer divider = 4 259 #define TIMER_DIV4_VALUE_500us 65536-2765 //2765*4/22118400 = 500 us // Timer divider = 4 260 #define TIMER_DIV16_VALUE_10ms 65536-13824 //1500*16/22118400 = 10 ms // Timer divider = 16 261 #define TIMER_DIV64_VALUE_30ms 65536-10368 //10368*64/22118400 = 30 ms // Timer divider = 64 262 #define TIMER_DIV128_VALUE_100ms 65536-17280 //17280*128/22118400 = 100 ms // Timer divider = 128 263 #define TIMER_DIV128_VALUE_200ms 65536-34560 //34560*128/22118400 = 200 ms // Timer divider = 128 264 #define TIMER_DIV256_VALUE_500ms 65536-43200 //43200*256/22118400 = 500 ms // Timer divider = 256 265 #define TIMER_DIV512_VALUE_1s 65536-43200 //43200*512/22118400 = 1 s // Timer divider = 512 266 #endif 267 #ifdef FOSC_240000 // if Fsys = 20 MHz 268 #define TIMER_DIV12_VALUE_10us 65536-20 //20*12/24000000 = 10 uS, // Timer divider = 12 269 #define TIMER_DIV12_VALUE_1ms 65536-2000 //2000*12/24000000 = 1 mS, // Timer divider = 12 270 #define TIMER_DIV12_VALUE_10ms 65536-20000 //2000*12/24000000 = 10 mS // Timer divider = 12 271 #define TIMER_DIV4_VALUE_10us 65536-60 //60*4/24000000 = 10 uS, // Timer divider = 4 272 #define TIMER_DIV4_VALUE_100us 65536-600 //600*4/24000000 = 100 us // Timer divider = 4 273 #define TIMER_DIV4_VALUE_200us 65536-1200 //1200*4/24000000 = 200 us // Timer divider = 4 274 #define TIMER_DIV4_VALUE_500us 65536-3000 //3000*4/24000000 = 500 us // Timer divider = 4 275 #define TIMER_DIV4_VALUE_1ms 65536-6000 //6000*4/24000000 = 1 mS, // Timer divider = 4 276 #define TIMER_DIV16_VALUE_10ms 65536-15000 //15000*16/24000000 = 10 ms // Timer divider = 16 277 #define TIMER_DIV64_VALUE_30ms 65536-11250 //11250*64/24000000 = 30 ms // Timer divider = 64 278 #define TIMER_DIV128_VALUE_100ms 65536-18750 //37500*128/24000000 = 200 ms // Timer divider = 128 279 #define TIMER_DIV128_VALUE_200ms 65536-37500 //37500*128/24000000 = 200 ms // Timer divider = 128 280 #define TIMER_DIV256_VALUE_500ms 65536-46875 //46875*256/24000000 = 500 ms // Timer divider = 256 281 #define TIMER_DIV512_VALUE_1s 65536-46875 //46875*512/24000000 = 1 s. // Timer Divider = 512 282 #endif 283 //-------------------- Timer0 function define -------------------- 284 #define TIMER1_MODE0_ENABLE TMOD&=0x0F 285 #define TIMER1_MODE1_ENABLE TMOD&=0x0F;TMOD|=0x10 286 #define TIMER1_MODE2_ENABLE TMOD&=0x0F;TMOD|=0x20 287 #define TIMER1_MODE3_ENABLE TMOD&=0x0F;TMOD|=0x30 288 //-------------------- Timer1 function define -------------------- 289 #define TIMER0_MODE0_ENABLE TMOD&=0xF0 290 #define TIMER0_MODE1_ENABLE TMOD&=0xF0;TMOD|=0x01 291 #define TIMER0_MODE2_ENABLE TMOD&=0xF0;TMOD|=0x02 292 #define TIMER0_MODE3_ENABLE TMOD&=0xF0;TMOD|=0x03 293 //-------------------- Timer2 function define -------------------- 294 #define TIMER2_DIV_4 T2MOD|=0x10;T2MOD&=0x9F 295 #define TIMER2_DIV_16 T2MOD|=0x20;T2MOD&=0xAF 296 #define TIMER2_DIV_32 T2MOD|=0x30;T2MOD&=0xBF 297 #define TIMER2_DIV_64 T2MOD|=0x40;T2MOD&=0xCF 298 #define TIMER2_DIV_128 T2MOD|=0x50;T2MOD&=0xDF 299 #define TIMER2_DIV_256 T2MOD|=0x60;T2MOD&=0xEF 300 #define TIMER2_DIV_512 T2MOD|=0x70 301 #define TIMER2_Auto_Reload_Delay_Mode T2CON&=~SET_BIT0;T2MOD|=SET_BIT7;T2MOD|=SET_BIT3 302 #define TIMER2_Compare_Capture_Mode T2CON|=SET_BIT0;T2MOD&=~SET_BIT7;T2MOD|=SET_BIT2 303 304 #define TIMER2_CAP0_Capture_Mode T2CON&=~SET_BIT0;T2MOD=0x89 305 #define TIMER2_CAP1_Capture_Mode T2CON&=~SET_BIT0;T2MOD=0x8A 306 #define TIMER2_CAP2_Capture_Mode T2CON&=~SET_BIT0;T2MOD=0x8B 307 308 //-------------------- Timer2 Capture define -------------------- 309 //--- Falling Edge ----- 310 #define IC0_P12_CAP0_FallingEdge_Capture CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4 311 #define IC1_P11_CAP0_FallingEdge_Capture CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x01;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4 312 #define IC2_P10_CAP0_FallingEdge_Capture CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x02;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4 313 #define IC3_P00_CAP0_FallingEdge_Capture CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x03;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4 314 #define IC3_P04_CAP0_FallingEdge_Capture CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x04;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4 315 #define IC4_P01_CAP0_FallingEdge_Capture CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x05;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4 316 #define IC5_P03_CAP0_FallingEdge_Capture CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x06;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4 317 #define IC6_P05_CAP0_FallingEdge_Capture CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x07;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4 318 #define IC7_P15_CAP0_FallingEdge_Capture CAPCON1&=0xFC;CAPCON3&=0xF0;CAPCON3|=0x08;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4 319 320 #define IC0_P12_CAP1_FallingEdge_Capture CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5 321 #define IC1_P11_CAP1_FallingEdge_Capture CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x10;CAPCON0|=SET_BIT5;CAPCON0|=SET_BIT5 322 #define IC2_P10_CAP1_FallingEdge_Capture CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x20;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5 323 #define IC3_P00_CAP1_FallingEdge_Capture CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x30;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5 324 #define IC3_P04_CAP1_FallingEdge_Capture CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x40;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5 325 #define IC4_P01_CAP1_FallingEdge_Capture CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x50;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5 326 #define IC5_P03_CAP1_FallingEdge_Capture CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x60;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5 327 #define IC6_P05_CAP1_FallingEdge_Capture CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x70;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5 328 #define IC7_P15_CAP1_FallingEdge_Capture CAPCON1&=0xF3;CAPCON3&=0x0F;CAPCON3|=0x80;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5 329 330 #define IC0_P12_CAP2_FallingEdge_Capture CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6 331 #define IC1_P11_CAP2_FallingEdge_Capture CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x10;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6 332 #define IC2_P10_CAP2_FallingEdge_Capture CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x20;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6 333 #define IC3_P00_CAP2_FallingEdge_Capture CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x30;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6 334 #define IC3_P04_CAP2_FallingEdge_Capture CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x40;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6 335 #define IC4_P01_CAP2_FallingEdge_Capture CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x50;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6 336 #define IC5_P03_CAP2_FallingEdge_Capture CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x60;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6 337 #define IC6_P05_CAP2_FallingEdge_Capture CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x70;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6 338 #define IC7_P15_CAP2_FallingEdge_Capture CAPCON1&=0x0F;CAPCON4&=0xF0;CAPCON4|=0x80;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6 339 340 //----- Rising edge ---- 341 #define IC0_P12_CAP0_RisingEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4; 342 #define IC1_P11_CAP0_RisingEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x01;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4; 343 #define IC2_P10_CAP0_RisingEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x02;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4; 344 #define IC3_P00_CAP0_RisingEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x03;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4; 345 #define IC3_P04_CAP0_RisingEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x04;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4; 346 #define IC4_P01_CAP0_RisingEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x05;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4; 347 #define IC5_P03_CAP0_RisingEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x06;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4; 348 #define IC6_P05_CAP0_RisingEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x07;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4; 349 #define IC7_P15_CAP0_RisingEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x01;CAPCON3&=0xF0;CAPCON3|=0x08;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4; 350 351 #define IC0_P12_CAP1_RisingEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0FCAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5; 352 #define IC1_P11_CAP1_RisingEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x10;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5; 353 #define IC2_P10_CAP1_RisingEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x20;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5; 354 #define IC3_P00_CAP1_RisingEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x30;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5; 355 #define IC3_P04_CAP1_RisingEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x40;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5; 356 #define IC4_P01_CAP1_RisingEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x50;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5; 357 #define IC5_P03_CAP1_RisingEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x60;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5; 358 #define IC6_P05_CAP1_RisingEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x70;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5; 359 #define IC7_P15_CAP1_RisingEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x04;CAPCON3&=0x0F;CAPCON3|=0x80;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5; 360 361 #define IC0_P12_CAP3_RisingEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6; 362 #define IC1_P11_CAP3_RisingEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x01;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6; 363 #define IC2_P10_CAP3_RisingEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x02;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6; 364 #define IC3_P00_CAP3_RisingEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x03;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6; 365 #define IC3_P04_CAP3_RisingEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x04;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6; 366 #define IC4_P01_CAP3_RisingEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x05;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6; 367 #define IC5_P03_CAP3_RisingEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x06;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6; 368 #define IC6_P05_CAP3_RisingEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x07;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6; 369 #define IC7_P15_CAP3_RisingEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x10;CAPCON4&=0xF0;CAPCON4|=0x08;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6; 370 371 //-----BOTH edge ---- 372 #define IC0_P12_CAP0_BothEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4 373 #define IC1_P11_CAP0_BothEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x01;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4 374 #define IC2_P10_CAP0_BothEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x02;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4 375 #define IC3_P00_CAP0_BothEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x03;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4 376 #define IC3_P04_CAP0_BothEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x04;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4 377 #define IC4_P01_CAP0_BothEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x05;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4 378 #define IC5_P03_CAP0_BothEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x06;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4 379 #define IC6_P05_CAP0_BothEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x07;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4 380 #define IC7_P15_CAP0_BothEdge_Capture CAPCON1&=0xFC;CAPCON1|=0x02;CAPCON3&=0xF0;CAPCON3|=0x08;CAPCON0|=SET_BIT4;CAPCON2|=SET_BIT4 381 382 #define IC0_P12_CAP1_BothEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5 383 #define IC1_P11_CAP1_BothEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x10;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5; 384 #define IC2_P10_CAP1_BothEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x20;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5; 385 #define IC3_P00_CAP1_BothEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x30;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5; 386 #define IC3_P04_CAP1_BothEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x40;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5; 387 #define IC4_P01_CAP1_BothEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x50;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5; 388 #define IC5_P03_CAP1_BothEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x60;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5; 389 #define IC6_P05_CAP1_BothEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x70;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5; 390 #define IC7_P15_CAP1_BothEdge_Capture CAPCON1&=0xF3;CAPCON1|=0x08;CAPCON3&=0x0F;CAPCON3|=0x80;CAPCON0|=SET_BIT5;CAPCON2|=SET_BIT5; 391 392 #define IC0_P12_CAP3_BothEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6; 393 #define IC1_P11_CAP3_BothEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x01;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6; 394 #define IC2_P10_CAP3_BothEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x02;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6; 395 #define IC3_P00_CAP3_BothEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x03;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6; 396 #define IC3_P04_CAP3_BothEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x04;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6; 397 #define IC4_P01_CAP3_BothEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x05;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6; 398 #define IC5_P03_CAP3_BothEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x06;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6; 399 #define IC6_P05_CAP3_BothEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x07;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6; 400 #define IC7_P15_CAP3_BothEdge_Capture CAPCON1&=0x0F;CAPCON1|=0x20;CAPCON4&=0xF0;CAPCON4|=0x08;CAPCON0|=SET_BIT6;CAPCON2|=SET_BIT6; 401 402 #define TIMER2_IC2_DISABLE CAPCON0&=~SET_BIT6 403 #define TIMER2_IC1_DISABLE CAPCON0&=~SET_BIT5 404 #define TIMER2_IC0_DISABLE CAPCON0&=~SET_BIT4 405 406 /***************************************************************************************** 407 * For PWM setting 408 *****************************************************************************************/ 409 //--------- PMW clock source select define --------------------- 410 #define PWM_CLOCK_FSYS CKCON&=0xBF 411 #define PWM_CLOCK_TIMER1 CKCON|=0x40 412 //--------- PWM clock devide define ---------------------------- 413 #define PWM_CLOCK_DIV_2 PWMCON1|=0x01;PWMCON1&=0xF9 414 #define PWM_CLOCK_DIV_4 PWMCON1|=0x02;PWMCON1&=0xFA 415 #define PWM_CLOCK_DIV_8 PWMCON1|=0x03;PWMCON1&=0xFB 416 #define PWM_CLOCK_DIV_16 PWMCON1|=0x04;PWMCON1&=0xFC 417 #define PWM_CLOCK_DIV_32 PWMCON1|=0x05;PWMCON1&=0xFD 418 #define PWM_CLOCK_DIV_64 PWMCON1|=0x06;PWMCON1&=0xFE 419 #define PWM_CLOCK_DIV_128 PWMCON1|=0x07 420 //--------- PWM I/O select define ------------------------------ 421 #define PWM5_P15_OUTPUT_ENABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1|=0x20;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP //P1.5 as PWM5 output enable 422 #define PWM5_P03_OUTPUT_ENABLE PIOCON0|=0x20 //P0.3 as PWM5 423 #define PWM4_P01_OUTPUT_ENABLE PIOCON0|=0x10 //P0.1 as PWM4 output enable 424 #define PWM3_P04_OUTPUT_ENABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1|=0x08;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP //P0.4 as PWM3 output enable 425 #define PWM3_P00_OUTPUT_ENABLE PIOCON0|=0x08 //P0.0 as PWM3 426 #define PWM2_P05_OUTPUT_ENABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1|=0x04;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP //P1.0 as PWM2 output enable 427 #define PWM2_P10_OUTPUT_ENABLE PIOCON0|=0x04 //P1.0 as PWM2 428 #define PWM1_P14_OUTPUT_ENABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1|=0x02;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP //P1.4 as PWM1 output enable 429 #define PWM1_P11_OUTPUT_ENABLE PIOCON0|=0x02 //P1.1 as PWM1 430 #define PWM0_P12_OUTPUT_ENABLE PIOCON0|=0x01 //P1.2 as PWM0 output enable 431 #define ALL_PWM_OUTPUT_ENABLE PIOCON0=0xFF;PIOCON1=0xFF 432 #define PWM5_P15_OUTPUT_DISABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1&=0xDF;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP //P1.5 as PWM5 output disable 433 #define PWM5_P03_OUTPUT_DISABLE PIOCON0&=0xDF //P0.3 as PWM5 434 #define PWM4_P01_OUTPUT_DISABLE PIOCON0&=0xEF //P0.1 as PWM4 output disable 435 #define PWM3_P04_OUTPUT_DISABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1&=0xF7;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP //P0.4 as PWM3 output disable 436 #define PWM3_P00_OUTPUT_DISABLE PIOCON0&=0xF7 //P0.0 as PWM3 437 #define PWM2_P05_OUTPUT_DISABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1&=0xFB;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP //P1.0 as PWM2 output disable 438 #define PWM2_P10_OUTPUT_DISABLE PIOCON0&=0xFB //P1.0 as PWM2 439 #define PWM1_P14_OUTPUT_DISABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;SFRS|=0x01;PIOCON1&=0xFD;TA=0xAA;TA=0x55;SFRS&=0xFE;EA=BIT_TMP //P1.4 as PWM1 output disable 440 #define PWM1_P11_OUTPUT_DISABLE PIOCON0&=0xFD //P1.1 as PWM1 441 #define PWM0_P12_OUTPUT_DISABLE PIOCON0&=0xFE //P1.2 as PWM0 output disable 442 #define ALL_PWM_OUTPUT_DISABLE PIOCON0=0x00;PIOCON1=0x00 443 //--------- PWM I/O Polarity Control --------------------------- 444 #define PWM5_OUTPUT_INVERSE PNP|=0x20 445 #define PWM4_OUTPUT_INVERSE PNP|=0x10 446 #define PWM3_OUTPUT_INVERSE PNP|=0x08 447 #define PWM2_OUTPUT_INVERSE PNP|=0x04 448 #define PWM1_OUTPUT_INVERSE PNP|=0x02 449 #define PWM0_OUTPUT_INVERSE PNP|=0x01 450 #define PWM_OUTPUT_ALL_INVERSE PNP=0xFF 451 #define PWM5_OUTPUT_NORMAL PNP&=0xDF 452 #define PWM4_OUTPUT_NORMAL PNP&=0xEF 453 #define PWM3_OUTPUT_NORMAL PNP&=0xF7 454 #define PWM2_OUTPUT_NORMAL PNP&=0xFB 455 #define PWM1_OUTPUT_NORMAL PNP&=0xFD 456 #define PWM0_OUTPUT_NORMAL PNP&=0xFE 457 #define PWM_OUTPUT_ALL_NORMAL PNP=0x00 458 //--------- PWM type define ------------------------------------ 459 #define PWM_EDGE_TYPE PWMCON1&=~SET_BIT4 460 #define PWM_CENTER_TYPE PWMCON1|=SET_BIT4 461 //--------- PWM mode define ------------------------------------ 462 #define PWM_IMDEPENDENT_MODE PWMCON1&=0x3F 463 #define PWM_COMPLEMENTARY_MODE PWMCON1|=0x40;PWMCON1&=0x7F 464 #define PWM_SYNCHRONIZED_MODE PWMCON1|=0x80;PWMCON1&=0xBF 465 #define PWM_GP_MODE_ENABLE PWMCON1|=0x20 466 #define PWM_GP_MODE_DISABLE PWMCON1&=0xDF 467 //--------- PMW interrupt setting ------------------------------ 468 #define PWM_FALLING_INT BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xCF;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 469 #define PWM_RISING_INT BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=0x10;PWMCON0&=0xDF;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 470 #define PWM_CENTRAL_POINT_INT BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=0x20;PWMCON0&=0xEF;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 471 #define PWM_PERIOD_END_INT BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC|=0x30;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 472 //--------- PWM interrupt pin select --------------------------- 473 #define PWM_INT_PWM0 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xF8;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 474 #define PWM_INT_PWM1 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xF8;PWMINTC|=0x01;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 475 #define PWM_INT_PWM2 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xF8;PWMINTC|=0x02;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 476 #define PWM_INT_PWM3 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xF8;PWMINTC|=0x03;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 477 #define PWM_INT_PWM4 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xF8;PWMINTC|=0x04;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 478 #define PWM_INT_PWM5 BIT_TMP=EA;TA=0xAA;TA=0x55;SFRS=0x01;PWMINTC&=0xF8;PWMINTC|=0x05;TA=0xAA;TA=0x55;SFRS=0x00;EA=BIT_TMP 479 //--------- PWM Dead time setting ------------------------------ 480 #define PWM45_DEADTIME_ENABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|=0x04;EA=BIT_TMP 481 #define PWM34_DEADTIME_ENABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|=0x02;EA=BIT_TMP 482 #define PWM01_DEADTIME_ENABLE BIT_TMP=EA;EA=0;TA=0xAA;TA=0x55;PDTEN|=0x01;EA=BIT_TMP 483 484 /***************************************************************************************** 485 * For ADC INIT setting 486 *****************************************************************************************/ 487 #define Enable_ADC_AIN0 ADCCON0&=0xF0;P17_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT0;ADCCON1|=SET_BIT0 //P17 488 #define Enable_ADC_AIN1 ADCCON0&=0xF0;ADCCON0|=0x01;P30_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT1;ADCCON1|=SET_BIT0 //P30 489 #define Enable_ADC_AIN2 ADCCON0&=0xF0;ADCCON0|=0x02;P07_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT2;ADCCON1|=SET_BIT0 //P07 490 #define Enable_ADC_AIN3 ADCCON0&=0xF0;ADCCON0|=0x03;P06_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT3;ADCCON1|=SET_BIT0 //P06 491 #define Enable_ADC_AIN4 ADCCON0&=0xF0;ADCCON0|=0x04;P05_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT4;ADCCON1|=SET_BIT0 //P05 492 #define Enable_ADC_AIN5 ADCCON0&=0xF0;ADCCON0|=0x05;P04_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT5;ADCCON1|=SET_BIT0 //P04 493 #define Enable_ADC_AIN6 ADCCON0&=0xF0;ADCCON0|=0x06;P03_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT6;ADCCON1|=SET_BIT0 //P03 494 #define Enable_ADC_AIN7 ADCCON0&=0xF0;ADCCON0|=0x07;P11_Input_Mode;AINDIDS=0x00;AINDIDS|=SET_BIT7;ADCCON1|=SET_BIT0 //P11 495 #define Enable_ADC_BandGap ADCCON0|=SET_BIT3;ADCCON0&=0xF8;ADCCON1|=SET_BIT0 //Band-gap 1.22V 496 497 #define PWM0_FALLINGEDGE_TRIG_ADC ADCCON0&=~SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1&=~SET_BIT3;ADCCON1&=~SET_BIT2;ADCCON1|=SET_BIT1 498 #define PWM2_FALLINGEDGE_TRIG_ADC ADCCON0&=~SET_BIT5;ADCCON0|=SET_BIT4;ADCCON1&=~SET_BIT3;ADCCON1&=~SET_BIT2;ADCCON1|=SET_BIT1 499 #define PWM4_FALLINGEDGE_TRIG_ADC ADCCON0|=SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1&=~SET_BIT3;ADCCON1&=~SET_BIT2;ADCCON1|=SET_BIT1 500 #define PWM0_RISINGEDGE_TRIG_ADC ADCCON0&=~SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1&=~SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1 501 #define PWM2_RISINGEDGE_TRIG_ADC ADCCON0&=~SET_BIT5;ADCCON0|=SET_BIT4;ADCCON1&=~SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1 502 #define PWM4_RISINGEDGE_TRIG_ADC ADCCON0|=SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1&=~SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1 503 #define PWM0_CENTRAL_TRIG_ADC ADCCON0&=~SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1|=SET_BIT3;ADCCON1&=~SET_BIT2;ADCCON1|=SET_BIT1 504 #define PWM2_CENTRAL_TRIG_ADC ADCCON0&=~SET_BIT5;ADCCON0|=SET_BIT4;ADCCON1|=SET_BIT3;ADCCON1&=~SET_BIT2;ADCCON1|=SET_BIT1 505 #define PWM4_CENTRAL_TRIG_ADC ADCCON0|=SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1|=SET_BIT3;ADCCON1&=~SET_BIT2;ADCCON1|=SET_BIT1 506 #define PWM0_END_TRIG_ADC ADCCON0&=~SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1|=SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1 507 #define PWM2_END_TRIG_ADC ADCCON0&=~SET_BIT5;ADCCON0|=SET_BIT4;ADCCON1|=SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1 508 #define PWM4_END_TRIG_ADC ADCCON0|=SET_BIT5;ADCCON0&=~SET_BIT4;ADCCON1|=SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1 509 510 #define P04_FALLINGEDGE_TRIG_ADC ADCCON0|=0x30;ADCCON1&=0xF3;ADCCON1|=SET_BIT1;ADCCON1&=~SET_BIT6 511 #define P13_FALLINGEDGE_TRIG_ADC ADCCON0|=0x30;ADCCON1&=0xF3;ADCCON1|=SET_BIT1;ADCCON1|=SET_BIT6 512 #define P04_RISINGEDGE_TRIG_ADC ADCCON0|=0x30;ADCCON1&=~SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1;ADCCON1&=~SET_BIT6 513 #define P13_RISINGEDGE_TRIG_ADC ADCCON0|=0x30;ADCCON1&=~SET_BIT3;ADCCON1|=SET_BIT2;ADCCON1|=SET_BIT1;ADCCON1|=SET_BIT6 514 515 /***************************************************************************************** 516 * For SPI INIT setting 517 *****************************************************************************************/ 518 #define SPICLK_DIV2 clr_SPR0;clr_SPR1 519 #define SPICLK_DIV4 set_SPR0;clr_SPR1 520 #define SPICLK_DIV8 clr_SPR0;set_SPR1 521 #define SPICLK_DIV16 set_SPR0;set_SPR1 522 #define Enable_SPI_Interrupt set_ESPI;set_EA 523 #define SS P15
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