Synopsys VCS 学习笔记

Posted 2020-07-19 宁静致远

1、VCS常用编译命令：
　　vcs source_files [source_or_object_files] options
e.g vcs top.v toil.v -RI +v2k

Details of Options:

-I:Compiles for interactive use

+v2k:Enables new language features in the proposed IEEE 1364-2001 standard. See “Implemented IEEE Std 1364-2001 Language Constructs” on page 2-23.

-R after compilation, run simulation executable

-RI after compilation, run simulation under xvcs

-sverilog
Enables the use of the Verilog language extensions in the Accellera
SystemVerilog specification.

-debug
Enables the use of UCLI commands and DVE.

-debug_all
Enables the use of UCLI and DVE. Also enables line stepping.

-doc

Starts browser to display the html files for the VCS/VCSi documentation.

-vcd <filename>
Sets the output VCD file name to the specified file.
The default filename is verilog.dump.
A $dumpfile system task in the Verilog source code will override
this option.

+vcdfile+<filename>
Specifies the VCD file you want to use for post-processing.

-fsdb
To dump an fsdb file

-Xman=4:combines all source files into a single file “tokens.v”
e.g:vcs add4.v top.v -Xman=4

-l filename:Specifies a file where VCS records compilation messages. If you
also enter the -R option, VCSrecords messages from both
compilation and simulation in the same file.

2、fsdbDumpfile and fsdbDumpvars to dump an fsdb file.
fsdbDumpfile - 指定FSDB文件名
-语法：$fsdbDumpfile("FSDB name")
-功能：将dump下来的资料存成指定的档案

fsdbDumpvars - Dump指定的变量
-语法：$fsdbDumpvars；$fsdbDumpvars(leval,module/var);
-功能：将所要观察的变量dump下来，存储到FSDB file.

$fsdbDumpon,$fsdbDumpfileoff
-功能：Turn on/off dump 变量的功能

$fsdbDumpMem,$fsdbDumpMenNow
-语法：$fsdbDumpMem,$fsdbDumpMemNow
-功能：将记忆体的值储存到FSDB file，当呼叫$fsdbDumpMemNow时记忆体的值会立即被dump出来，而呼叫$fsdbDumpMem则必须等到时机间隔结束才会dump出来。

example 1:

1 initial begin
2 　　$vcdpluson;
3 　　$fsdbDumpfile("test.fsdb");
4 　　$fsdbDumpvars(0,router_test_io);
5 end

 

example 2:

1 initial begin
2     $vcdpluson;
3     $fsdbDumpfile("test.fsdb");
4     $fsdbDumpvars(0,test);
5 end

 

注：example 1和example 2将router_test_io和test两个模块中的信号波形全部存在test.sfdb文件中。

3、执行simv(VCS生成仿真使用的二进制测试文件)文件
命令：./simv [run_time_options]

run_time_options

-s： stops simulation at time 0

e.g:./simv -s

4、Interactive mode(交互模式)
允许实时的控制仿真的进行，允许在模拟的过程中改变寄存器的值或者设置，这些改变会实时地影响到模拟的结果

5、Post-processing mode(后台处理方式)
先输出用户指定选择的信号及其变化过程到一个文件中，然后可以用 VirSim来分析这个文件。该文件是 VCD+类型的，VCD+文件是一种二进制的格式，里面记录了 VCS模拟的结果，和信号的变化历史等信息。

6、VCS编译注意问题：
使用VCS编译时，必须先将含有`timescale或者宏定义的文档放在前面，不然会报错误
Error-[ITSFM] Illegal `timescale for module
router_test_top.sv, 7
Module "router_test_top" has `timescale but previous module(s)/package(s) do
not.
Please refer LRM 1364-2001 section 19.8.