MT6235

Posted 2021-01-28 kwincaq

 
MT6235 is capable of running the ARM926EJ-S(32-bit) RISC processor at up to 208 MHz, thus providing fast data processing capabilities. In addition to the high clock frequency, separate CODE and DATA caches are also included to further improve the overall system efficiency.

Platform Features  
1)General:
Integrated voice-band, audio-band and base-band analog front ends
TFBGA 13mm!¨￠13mm, 362-ball, 0.5 mm pitch package
 
2)MCU Subsystem
ARM926EJ-S 32-bit RISC processor
High performance multi-layer AMBA bus
Java hardware acceleration for fast Java-based games and applets
Operating frequency: 26/52/104/208 MHz
Dedicated DMA bus
14 DMA channels
512K bits on-chip SRAM
384K bits Instruction-TCM
640K bits Data-TCM
128K bits Instruction-Cache
128K bits Data-Cache
On-chip boot ROM for Factory Flash Programming
Watchdog timer for system crash recovery
3 sets of General Purpose Timer
Circuit Switch Data coprocessor
Division coprocessor
PPP Framer coprocessor

3)External Memory Interface
 
Supports up to 4 external memory devices
Supports 8-bit or 16-bit memory components with maximum size of up to 128M Bytes each
Supports Mobile SDRAM and Cellular RAM
Supports Flash and SRAM/PSRAM with page mode or burst mode
Industry standard Parallel LCD interface
Supports multi-media companion chips with 8/16 bits data width
Flexible I/O voltage of 1.8V ~ 2.8V for memory interface
Configurable driving strength for memory interface 

4)User Interfaces
 8-row !¨￠ 8-column keypad controller with hardware scanner
Supports multiple key presses for gaming
SIM/USIM controller with hardware T=0/T=1 protocol control
Real Time Clock (RTC) operating with a separate power supply
General Purpose I/Os (GPios)
4 sets of Pulse Width Modulation (PWM) output
Alerter output with Enhanced PWM or PDM
8 external interrupt lines
 
5)Security
Supports security key and 126 bit chip unique ID

6)Connectivity
3 UARTs with hardware flow control and speeds up to 921600 bps
IrDA modulator/demodulator with hardware framer.  Supports SIR/MIR/FIR operating speeds.
USB 2.0 capability
Multi Media Card, Secure Digital Memory Card, Memory Stick, Memory Stick Pro host controller with flexible I/O voltage power
Supports SDIO interface for SDIO peripherals as well as WIFI connectivity  
DAI/PCM and I2S interface for Audio application

7)Power Management 
Power Down Mode for analog and digital circuits  
Processor Sleep Mode  
Pause Mode of 32 KHz clocking in Standby State  
4-channel Auxiliary 10-bit A/D Converter for charger and battery monitoring and photo sensing  

8)Test and Debug
Built-in digital and analog loop back modes for both Audio and Baseband Front-End  
DAI port complying with GSM Rec.11.10  
JTAG port for debugging embedded MCU

 General Description
MT6235 based on a dual-processor architecture, MT6235 integrates both an ARM926EJ-S core and a digital signal processor core. ARM926EJ-S is the main processor responsible for running high-level GSM/GPRS protocol software as well as multi-media applications. The digital signal processor manages the low-level MODEM as well as advanced audio unctions. Except for a few mixed-signal circuitries, the other building blocks in MT6235 are connected to either the microcontroller or the digital signal processor.

MT6235consists of the following subsystems:  
Microcontroller Unit (MCU) Subsystem: includes an ARM926EJ-S RISC processor and its accompanying memory management and interrupt handling logics;  
Digital Signal Processor (DSP) Subsystem: includes a DSP and its accompanying memory, memory controller, and interrupt controller;  
MCU/DSP Interface: the junction at which the MCU and the DSP exchange hardware and software information;  
Microcontroller Peripherals: includes all user interface modules and RF control interface modules;  
Microcontroller Coprocessors: runs computing-intensive processes in place of the Microcontroller;  
DSP Peripherals: hardware accelerators for GSM/GPRS/EDGE channel codec;  
Multi-media Subsystem: integrates several advanced accelerators to support multi-media applications;  
Voice Front End: the data path for converting analog speech to and from digital speech;
Audio Front End: the data path for converting stereo audio from an audio source;  
Baseband Front End: the data path for converting a digital signal to and from an analog signal from the RF modules; 
Timing Generator: generates the control signals related to the TDMA frame timing; and, 
Power, Reset and Clock Subsystem: manages the power, reset, and clock distribution inside MT6235.

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