重学Veriliog——高级编程语句

Posted 2021-01-09 genxgss

1.判断

1.1 if ... else ...

• 有优先级
• 在组合逻辑电路中，需要避免产生Latch(避免结构不完整)
• Latch容易引起竞争冒险，同时静态时序分析工具也不好分析穿过Latch的路径？

1.2 case

• 无优先级
• 使用default，防止latch

1.3 casex和casez

• casez将分支中所有的z看作不“care”的值

casez (encoder)
    4‘b1???: high_lvl = 3;
    4‘b01??: high_lvl = 2;
    4‘b001?: high_lvl = 1;
    4‘b0001: high_lvl = 0;
    default : high_lvl = 0;
endcase

 

• casex将分支中所有的z和x看作不“care”的值

casez (encoder)
    4‘b1xxx: high_lvl = 3;
    4‘b01xx: high_lvl = 2;
    4‘b001x: high_lvl = 1;
    4‘b0001: high_lvl = 0;
    default : high_lvl = 0;
endcase

 

2.循环

2.1 forever

initial
begin
clk = 0;
forver #25 clk = ~clk;
end

生成了50 的时钟

2.2 repeat

if (rotate == 1)
    repeat(8)
        begin
            tmp = data[15];
            data = {data << 1,tmp};
        end

重复8次

2.3 while

1 initial
2 begin
3     count = 0;
4     while (count < 101)
5     begin
6         $ display ("Count = %d" , count);
7         count = count + 1;
8     end
9 end

 

 2.4 for

 1 integer i;
 2 always @(inp or cnt)
 3 begin
 4     result[7:4] = 0;
 5     result[3:0] = inp;
 6     if (cnt == 1)
 7     begin
 8     for (i = 4; i  <= 7; i=i+1)
 9         begin
10             result[i]=result[i - 4];
11         end
12     result[3:0] = 0;
13     end
14 end