Modelsim自动化仿真之do文件书写

Posted 2021-01-03 bitrocco

do 文件书写

1. 创建本地库

   vlib ./work

   You must use vlib rather than operating system commands to creat a library directory or index file.

2. 映射逻辑库到物理目录

   vmap work ./work

3. 编译源代码（缺省编译到 work 本地库）

   vlog ./../design/*.v

   vlog ./tb_div_odd.v

   可以使用 "- work" 指定编译到哪个库中

4. 启动仿真器

   vsim -voptargs=+acc work.tb_div_odd

5. 添加波形

   add wave tb_div_odd/*

6. 执行仿真

   run -all

示例 run.do 文件如下所示：

# 退出当前仿真
quit  -sim

# 清输出窗口
.main clear

# 创建本地库
# You must use vlib rather than operating system commands to creat a library directory or index file.
vlib  ./work
vlib  ./altera_lib

# 将逻辑库名映射库路径
vmap  work        ./work
vmap  alt_lib     ./altera_lib

# 编译 verilog 源代码
# 其中的 "- work" 参数用来具体指定将 verilog 源代码编译到哪个库中，缺省编译到 work 库
vlog  -work  alt_lib     ./altera_mf.v
vlog  -work  alt_lib     ./../quartus_prj/ipcore_dir/pll_1.v
vlog  -work  work        ./../design/*.v
vlog  -work  work        ./tb_ipcore_pll.v

# 启动仿真器
vsim  -voptargs=+acc  -L alt_lib  -L work  work.tb_ipcore_pll

# 添加波形
add   wave   tb_ipcore_pll/*

# 执行仿真
run   1us

参考 run.do 文件如下所示：

vsim    -t ns -voptargs=+acc  -L design -L base_space base_space.*.v
# -t    运行仿真的精度是ns
# -L    链接库关键字
========================================================================
虚拟信号

#前面数字书写默认为10进制
virtual type {
{01 IDLE}
{02 A}
{04 B}
{08 C}
{16 D}
{32 E}
} vir_new_signal

virtual function {
(vir_new_signal)tb_seq_det/seq_det_inst/state
} new_state

add  wave  tb_seq_det/seq_det_inst/new_state
========================================================================
quit   -sim
.main  clear

vlib   ./lib/
vlib   ./lib/work/
vmap   work ./lib/work/

vlog   -work  work  ./tb_shift_reg.v
vlog   -work  work  ./../design/shift_reg.v

vsim   -voptargs=+acc  work.tb_shift_reg

add    wave  tb_shift_reg/clk
add    wave  tb_shift_reg/rst_n
add    wave  tb_shift_reg/mem1x16
add    wave  tb_shift_reg/i_30
add    wave  tb_shift_reg/i_data
add    wave  tb_shift_reg/shift_reg_inst/shift_reg
add    wave  tb_shift_reg/shift_reg_inst/s_cnt
add    wave  tb_shift_reg/shift_reg_inst/s_flag
add    wave  tb_shift_reg/shift_reg_inst/s_flag_delay
add    wave  tb_shift_reg/shift_reg_inst/o_data
add    wave  tb_shift_reg/o_data

run    10us
==========================================================================
virtual.do

virtual type { {0x1 IDLE}{0x2 A}{0x4 B}{0x8 C}{0x10 D}{0x20 E}} vir_new_signal
virtual function -install /tb_seq_det/seq_det_inst -env /tb_seq_det { (vir_new_signal)tb_seq_det/seq_det_inst/state} new_state
==========================================================================
后仿真

quit   -sim
.main  clear

vlib   ./lib/
vlib   ./lib/work/
vlib   ./lib/altera_lib/
vmap   work ./lib/work/
vmap   altera_lib ./lib/altera_lib/

vlog   -work  work          ./tb_seq_det.v
vlog   -work  work          ./../design/*.vo
vlog   -work  altera_lib    ./altera_lib/*.v

vsim   -t ns -sdfmax tb_seq_det/seq_det_inst=seq_det_v.sdo -voptargs=+acc -L altera_lib work.tb_seq_det

add     wave  tb_seq_det/*

run    10us