makefile_basic
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#****************Top invoking********************
all: com sim
#*****************Variable***********************
OUTPUT = USB_Dual_Port
#ALL_DEFINE = +define+DUMP_VPD
#Code coverage command
#CM = -cm line+cond+fsm+branch+tgl
CM = -cm line+cond+fsm+branch
#*****************Invoking Var*******************
CM_NAME = -cm_name $(OUTPUT)_case2
CM_DIR = -cm_dir ./$(OUTPUT).vdb
#post-simulaiton
LIB_EXT = +libext+.v
LIB_FILE = -v /export/home1/user2/asic209b/library/HDSCL1NMV1_v1.3/LIB
#vpd file name
VPD_NAME = +vpdfile+$(OUTPUT).vpd
#This 2 compile time switch should turn off
#when post-simulaiton is on going.
# +notimingcheck
# +nospecify
#Compile command
VCS = vcs -sverilog +v2k
-debug_all
+notimingcheck
+nospecify
+vcs+flush+all
$(CM)
$(CM_NAME)
$(CM_DIR)
$(ALL_DEFINE)
$(VPD_NAME)
-o $(OUTPUT)
-l compile.log
# $(LIB_EXT)
# $(LIB_FILE)
# -timescale=100ns/1ns
#simulaiton command
SIM = ./$(OUTPUT)
$(CM) $(CM_NAME) $(CM_DIR)
$(VPD_NAME)
-l $(OUTPUT).log
#SIM = ./$(OUTPUT) -cm line+cond+fsm+branch +Test2 -cm_name Test2
#Start compile
com:
$(VCS) -f verif.f
#Start simulaiton
sim:
$(SIM)
#Run gui
run:
$(VCS) -f verif.f -R -l $(OUTPUT).log -gui &
#Show the coverage
cov:
dve -covdir *.vdb &
urg:
urg -dir *.vdb -dbname mergedir/merged
#./$(OUTPUT) -cm line+cond+fsm+branch +Test1 -cm_name Test1
#Show the waves
debug:
dve -vpd $(OUTPUT).vpd &
#Start clean
clean:
@rm -rf csrc DVEfiles $(OUTPUT) *.daidir ucli.key VCS*
@rm -rf *.log *.vpd *.ddc *.svf *.SDF *Synth *Netlist*
@rm -rf alib-52 *Report
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