三态门实现“一读多写”总线结构

Posted 2020-12-26 shaonianpi

 1 //三态门完成总线选择功能
 2 module tri_state_gate(input request0,request1,request2,request3,input[7:0] unit0_out,unit1_out,unit2_out,unit3_out,
 3  output[7:0]unit0_in,unit1_in,unit2_in,unit3_in);
 4  reg[7:0]bus;
 5  reg[3:0] en;
 6 always@(request0,request1,request2,request3)
 7 begin 
 8     casex({request0,request1,request2,request3})
 9     4‘b0001:en=4‘b0001;    //注意，这里区别于MUX结构对于三态门而言，每个门电路都有自己的使能端
10     4‘b001x:en=4‘b0010;
11     4‘b01xx:en=4‘b0100;
12     4‘b1xxx:en=4‘b1000;
13     default:
14     en=4‘b0000;
15     endcase
16 end
17 //写总线
18 always@(en,unit0_out,unit1_out,unit2_out,unit3_out)
19 begin 
20     case(en)
21          4‘b0001:bus=unit0_out;
22          4‘b0010:bus=unit1_out;
23          4‘b0100:bus=unit2_out;
24          4‘b1000:bus=unit3_out;
25         default:
26         bus=8‘hzz;  //总线空闲的时候，处于断开的状态，属于高阻态，这个特性很重要！
27     endcase
28 end        
29 assign unit0_in=bus;
30 assign unit1_in=bus;
31 assign unit2_in=bus;
32 assign unit3_in=bus;
33 endmodule