verilog code slice学习成长纪念

Posted 2020-12-25 luoyanghero

//=== 1.high pulse to(2) high level
`ifndef DLY       
`define DLY 1     
`endif            
//only for sync clk signal.
module PUL2LVL_H (/*autoarg*/
    //Inputs
    clk_bus, brst_n, sig_in, 

    //Outputs
    sig_out);

parameter  DW = 10;

input  clk_bus;//clock
input  brst_n;//reset
input  sig_in;
output  sig_out;
reg  [DW-1:0]     sig_dly;    
wire              sig_out;    

always @(posedge clk_bus or negedge brst_n) begin
    if (!brst_n) begin
        sig_dly[DW-1:0] <= #`DLY ‘b0;
    end
    else begin
        sig_dly[DW-1:0] <= #`DLY {sig_dly[DW-2:0],sig_in};
    end
end
assign sig_out = |sig_dly | sig_in;
endmodule

//最初写过的生涩的code，仅此保留已做纪念。
//replace keyword 
//eg:r_keyword_p2l_cnt -> r_aaaa_p2l_cnt
////================= fresh version
//reg [6:0] r_keyword_p2l_cnt;
//reg r_keyword_hl;
//wire w_keyword_p2l_cnt_eq_keyword_size_1;
//assign w_keyword_p2l_cnt_eq_keyword_size_1 = r_keyword_p2l_cnt == w_keyword_size_1;
//always @(posedge i_clk or negedge i_rst_n)begin
//    if (!i_rst_n) begin
//        r_keyword_hl <= 1‘b0;
//    end
//    else begin
//        if(i_keyword_condition) begin
//            r_keyword_hl <= 1‘b1;
//        end
//        else if(w_keyword_p2l_cnt_eq_keyword_size_1) begin
//            r_keyword_hl <= 1‘b0;
//        end
//        else begin
//            r_keyword_hl <= r_keyword_hl;
//        end
//    end
//end
//always @(posedge i_clk or negedge i_rst_n)begin
//    if (!i_rst_n) begin
//        r_keyword_p2l_cnt <= 7‘h0;
//    end
//    else begin
//        if(w_keyword_p2l_cnt_eq_keyword_size_1)begin
//            r_keyword_p2l_cnt <= 7‘h0;
//        end
//        else if(r_keyword_hl)begin
//            r_keyword_p2l_cnt <= r_keyword_p2l_cnt + 1‘b1;
//        end
//        else begin
//            r_keyword_p2l_cnt <= r_keyword_p2l_cnt;
//        end
//    end
//end
////================= 


//=== 2.delay match, this style is suitable for >10 delay (not usually use)
//dly延迟很简单，直接打寄存器，不需要这么复杂。以下code仅做纪念。
////replace: _keyword _condition1 _condition2
////eg: j_keyword -> j_aaaaaaaa
//localparam DELAY_keyword = 19;
//genvar j_keyword;
//generate 
//    for(j_keyword = 0; j_keyword < DELAY_keyword; j_keyword= j_keyword + 1)begin:dly_keyword
//        reg r_keyword_delay;
//        if(j_keyword == 0)begin
//            [email protected](posedge i_clk or negedge i_rst_n)
//            if(!i_rst_n)begin
//                r_keyword_delay <= 1‘d0;
//            end
//            else begin
//                dly_keyword[j_keyword].r_keyword_delay <= i_keyword; 
//            end
//        end
//        else begin
//            [email protected](posedge i_clk or negedge i_rst_n)
//            if(!i_rst_n)begin
//                r_keyword_delay <= 1‘d0;
//            end
//            else begin
//                dly_keyword[j_keyword].r_keyword_delay <= dly_keyword[j_keyword-1].r_keyword_delay; 
//            end
//        end
//    end
//endgenerate
////choose a specified delay from a delay array according to a condition
//reg r_keyword_dly;
//always @(posedge i_clk or negedge i_rst_n)begin
//    if (!i_rst_n) begin
//        r_keyword_dly <= 1‘d0;
//    end
//    else begin
//        if(i_condition1) begin
//            r_keyword_dly <= dly_keyword[PAR_condition1 -1].r_keyword_delay;
//        end
//        else if(i_condition2) begin
//            r_keyword_dly <= dly_keyword[PAR_condition2 -1].r_keyword_delay;
//        end
//    end
//end


//=== 3.produce a rise edge of a given signal
//replace _keyword
wire w_keyword_rsdg ;
reg r_keyword_r1 ;
always @(posedge i_clk or negedge i_rst_n)begin
    if (!i_rst_n) begin
        r_keyword_r1 <= 1‘b0;
    end
    else begin
        r_keyword_r1 <= w_keyword;
    end
end
assign w_keyword_rsdg = w_keyword & !r_keyword_r1;

 

有符号数相加要把位宽补齐再加（verilog-1995）

wire[7:0] a, b;
wire[8:0] sum1;
wire[9:0] sum2;
assign sum1 = {a[7],a} + {b[7],b};
assign sum2 = {sum1[8],sum1} + 10‘d23;

若为verilog-2001，可直接用signed关键字

wire signed [7:0] a, b;
wire signed [8:0] sum1;
wire signed [9:0] sum2;
assign sum1 = a + b;
assign sum2 = sum1 + 10‘d23;

其实对于硬件，没有符号这么一说，都是二进制数。使用verilog-1995写法更通用。

Q:why design compiler 2010 think this is not right?
A:Because i_wghtGridH is a variable.

integer i,j;
always @(posedge i_clk or negedge i_rst_n)begin
    if(!i_rst_n)begin
        for(i = 0; i < i_wghtGridH; i = i + 1)begin
            for(j = 0; j < i_wghtGridW; j = j + 1)begin
                r_WeightoNWeights0a[i][j] <= 5‘d0;
            end
        end
    end
    else begin
        r_WeightoNWeights0a[texel_cnt_y_r2][texel_cnt_x_r2] <= w_WeightoNWeights0;
    end 
end
//This is ok.
reg [4:0] r_WeightoNWeights0a [7:0][7:0];
integer i,j;
always @(posedge i_clk or negedge i_rst_n)begin
    if(!i_rst_n)begin
        for(i = 0; i < 8; i = i + 1)begin //num_plp can use wire ??
            for(j = 0; j < 8; j = j + 1)begin
                r_WeightoNWeights0a[i][j] <= 5‘d0;
            end
        end
    end
    else begin
        r_WeightoNWeights0a[texel_cnt_y_r2][texel_cnt_x_r2] <= w_WeightoNWeights0;
    end
end