VIVADO
Posted alke-95
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VIVADO 流程：
input：verilog/VHDL/System Verilog /IP/DSP/uP;
synthesis：synth_design、report_timing_summary;
implementation：opt_design、place_design、route_design、report_timing_summary;
generate bit 。
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synth_design :3rd party EDIF、XDC;
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synth_design、opt_design、place_design、route_design =======>Design Checkpoint (.dcp);
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top.dcp top_opt.dcp top_placed.dcp top_routed.dcp
Design Checkpoint include：EDIF、XDC、XDEF;
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VIVADO 以IP为核心设计：
IP Catalog
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VIVADO 共享数据库（.dcp）
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