synopsys dw_axi_dmac 使用集成经验

Posted 2023-05-20 light-weight-ip

总体简介

AHB/APB用于寄存器配置和访问，2个AXI Master port用于实现数据src和dst的搬运，带perh请求握手接口，独立的debug interface，中断接口

主要特性

▲共32个channel，每个通道都对应一对src和dst
▲每个channel都是单向的
▲2个AXI Master支持多层级连接访问
▲mem2mem,mem2perh,perh2mem,perh2perh
▲端模式可选，可引脚选择
▲仲裁可lock
▲内部状态output pin指示，最后一次写传输output pin指示
▲支持AXI非对其传输
▲低功耗配置
▲channel的ID，独立可配，每个channel都带单FIFO，深度可配。

通道控制

busrt transfer size
channel priority 可配置
链表传输模式

dma一般都不支持wrapping传输

一些参数描述

DMAX_UNALIGNED_XFER_EN非对其传输
DMAX_CH_ABORT_EN通道异常停止使能
DMAX_CH_MEM_EXT支持外部SRAM，FIFO memory
DMAX_MSTIF_MODE为AXI版本选择
AXI参数配置
DMAX_SLVIF_MODE配置模式选择参数
DMAX_SAFETY_FEATURE_EN ECC校验功能。
低功耗相关参数配置

感悟

因为整个DMAC的功能比较全，所以其面积也不小，因此在配置时，注意结合自己需求来配置，比如假如配置接口和主时钟本来就是同步的，那就没必要配成异步，否者会在同步处理上耗费大量寄存器，若是在消费量产品上面，也没必要打开AXI Safety特性，根据实际数据最大长度，配置busrt的长度。DEBUG过程中，抓住数据流向。

附录A：Synopsys Design Constraints(SDC)

文章目录

• • A.1 基本命令(Basic Commands)
  • A.2 对象访问命令(Object Access Commands)
  • A.3 时序约束(Timing Constraints)
  • A.4 环境命令(Environment Commands)
  • A.5 多电压命令(Multi-Voltage Commands)

---

本附录将介绍1.7版本的$SDC(SynopsysDesignConstraints)$格式，此格式主要用于指定设计的时序约束。它不包含任何特定工具的命令，例如链接（link）和编译（compile）。它是一个文本文件，可以手写或由程序创建，并由程序读取。某些$SDC$命令仅适用于实现（implementation）或综合（synthesis），但是本附录会列出所有$SDC$命令。

$SDC$语法是基于$TCL$的格式，即所有命令都遵循$TCL$语法。一个$SDC$文件会在文件开头包含$SDC$版本号，其次是设计约束，注释（注释以字符＃开始，并在行尾处结束）在$SDC$文件中可以散布在设计约束中。设计约束中较长的命令行可以使用反斜杠（\\）字符分成多行。

---

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A.1 基本命令(Basic Commands)

以下是基本的$SDC$命令：

=========================================================================
current_instance [instance_pathname]
# Sets the current instance of design. This allows other
# commands to set or get attributes from that instance.
# If no argument is supplied, then the current instance
# becomes the top-level.
Examples:
	current_instance /core/U2/UPLL
	current_instance .. # Go up one hierarchy.
	current_instance # Set to top.
=========================================================================	
expr arg1 arg2 . . . argn
=========================================================================
list arg1 arg2 . . . argn
=========================================================================
set variable_name value
=========================================================================
set_hierarchy_separator separator
# Specifies the default hierarchy separator used within
# the SDC file. This can be overridden by using the -hsc
# option in the individual SDC commands where allowed.
Examples:
	set_hierarchy_separator /
	set_hierarchy_separator .
=========================================================================
set_units [-capacitance cap_unit] [-resistance res_units]
	[-time time_unit] [-voltage voltage_unit]
	[-current current_unit] [-power power_unit]
# Specifies the units used in the SDC file.
Examples:
	set_units -capacitance pf -time ps
=========================================================================

---

---

A.2 对象访问命令(Object Access Commands)

以下命令指明了如何访问一个设计实例中的对象：

=========================================================================
all_clocks
# Returns a collection of all clocks.
Examples:
	foreach_in_collection clkvar [all_clocks] 
	. . .
	
	set_clock_transition 0.150 [all_clocks]
=========================================================================	
all_inputs [-level_sensitive] [-edge_triggered]
	[-clock clock_name]
# Returns a collection of all input ports in the design.
Example:
	set_input_delay -clock VCLK 0.6 -min [all_inputs]
=========================================================================
all_outputs [-level_sensitive] [-edge_triggered]
[-clock clock_name]
# Returns a collection of all output ports in the design.
Example:
	set_load 0.5 [all_outputs]
=========================================================================
all_registers [-no_hierarchy] [-clock clock_name]
	[-rise_clock clock_name] [-fall_clock clock_name]
	[-cells] [-data_pins] [-clock_pins] [-slave_clock_pins]
	[-async_pins] [-output_pins] [-level_sensitive]
	[-edge_triggered] [-master_slave]
# Returns the set of registers with the properties
# as specified, if any.
Examples:
	all_registers -clock DAC_CLK
	# Returns all registers clocked by clock DAC_CLK.
=========================================================================	
current_design [design_name]
# Returns the name of the current design. If specified with
# an argument, it sets the current design to the one
# specified.
Examples:
	current_design FADD # Sets the current context to FADD.
	current_design # Returns the current context.
=========================================================================	
get_cells [-hierarchical] [-hsc separator] [-regexp]
	[-nocase] [-of_objects objects] patterns
# Returns a collection of cells in the design that match the
# specified pattern. Wildcard can be used to match
# multiple cells.
Examples:
	get_cells RegEdge* # Returns all cells that
					   # match pattern.
	foreach_in_collection cvar [get_cells -hierarchical *] 
		. . .
	 # Returns all cells in design by searching
	  # recursively down the hierarchy.
=========================================================================	  
get_clocks [-regexp] [-nocase] patterns
# Returns a collection of clocks in the design that match
# the specified pattern. When used in context such as -from
# or -to, it returns a collection of all flip-flops driven
# by the specified clocks.
Examples:
	set_propagated_clock [get_clocks SYS_CLK]
	set_multicycle_path -to [get_clocks jtag*]
=========================================================================
get_lib_cells [-hsc separator] [-regexp] [-nocase] patterns
# Creates a collection of library cells that are currently
# loaded and those that match the specified pattern.
Example:
	get_lib_cells cmos13lv/AOI3*
=========================================================================	
get_lib_pins [-hsc separator] [-regexp] [-nocase] patterns
# Returns a collection of library cell pins that match the
# specified pattern.
=========================================================================
get_libs [-regexp] [-nocase] patterns
# Returns a collection of libraries that are currently
# loaded in the design.
=========================================================================
get_nets [-hierarchical] [-hsc separator] [-regexp]
[-nocase] [-of_objects objects] patterns
# Returns a collection of nets that match the specified
# pattern.
Examples:
	get_nets -hierarchical * # Returns list of all nets in
		# design by searching recursively down the hierarchy.
	get_nets FIFO_patt*
=========================================================================	
get_pins [-hierarchical] [-hsc separator] [-regexp]
	[-nocase] [-of_objects objects] patterns
# Returns a collection of pin names that match the
# specified pattern.
Examples:
	get_pins *
	get_pins U1/U2/U3/UAND/Z
=========================================================================
get_ports [-regexp] [-nocase] patterns
# Returns a collection of port names (inputs and outputs)
# of design that match the specified pattern.
Example:
	foreach_in_collection port_name [get_ports clk*] 
	# For all ports that start with “clk”.
	. . .
	
=========================================================================

可以在不“获取”对象的情况下引用诸如端口（port）之类的对象吗？当设计中只有一个具有该名称的对象时，实际上没有任何区别。但是，当多个对象具有相同的名称时，使用get_ *命令将变得更加重要，它可以避免在引用哪种类型对象方面所带来的任何可能的混淆。假设有一个名为$BIST\_N1$的网络和一个名为$BIST\_N1$的端口，考虑以下$SDC$命令：

set_load 0.05 BIST_N1

问题是要引用哪个$BIST\_N1$？网络还是端口？在大多数情况下，最好明确表明对象的类型，例如：

set_load 0.05 [get_nets BIST_N1]

现在再假设有一个时钟$MCLK$和另一个也称为$MCLK$的端口，考虑以下 S D C SDC SDC<