你好。请问这个VHDL程序的测试程序要如何写？要在modelsim里运行的。。

Posted 2023-03-25

8位移位寄存器的程序：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SHFT IS
PORT ( CLK, LOAD : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
QB : OUT STD_LOGIC );
END SHFT;
ARCHITECTURE behav OF SHFT IS
SIGNAL REG8 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS (CLK, LOAD)
BEGIN
IF CLK'EVENT AND CLK = '1' THEN
IF LOAD ='1' THEN REG8 <= DIN;
ELSE REG8(6 DOWNTO 0) <= REG8(7 DOWNTO 1);
END IF;
END PROCESS;
QB <= REG8(0); DOUT<=REG8;
END behav;

我要在modelsim里进行波形的时序分析，可貌似没有测试程序的话就仿真不了。。。谁能帮我写下测试程序吗？？万分感激！！！

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity top is
port(DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
QB : OUT STD_LOGIC);
end top;

use work.all;
architecture Behavioral of top is
constant clk_period:time:=20 ns;
signal CLK,LOAD: STD_LOGIC;
signal DIN: STD_LOGIC_VECTOR(7 DOWNTO 0);
component shft
port(CLK,LOAD:IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
QB : OUT STD_LOGIC );
end component;
begin
g1:shft port map(clk,load,din,dout,qb);
clk_en:process
begin
clk<='1';
wait for clk_period/2;
clk<='0';
wait for clk_period/2;
end process;
en:process
begin
din<="10101010";
load<='1' after 40 ns,
'0' after 80 ns,
'1' after 120 ns,
'0' after 160 ns,
'1' after 200 ns,
'0' after 240 ns,
'1' after 280 ns,
'0' after 320 ns,
'1' after 360 ns;
wait;
end process;
end Behavioral; 参考技术A 首先，你这个程序少了个END IF;
一般都是直接编译然后时序分析，怎么会没有测试程序呢？我用的是max plus ii
至于不能测试，你封装一下然后做元件使，新建个DGF的电路图不就完了么。 参考技术B modelsim里直接输入测试波形吧
testbench用在简单的程序上有点麻烦