systemverilog 断言中assume 和assert的区别
Posted
tags:
篇首语:本文由小常识网(cha138.com)小编为大家整理,主要介绍了systemverilog 断言中assume 和assert的区别相关的知识,希望对你有一定的参考价值。
参考技术A assume用于做formal verification,如果输入和assume不一样,会出错, 断言(assert)可以用来检查行为或者时序的正确性。Mentor 的文档说的比较清楚
Example 2-7 defines two cut points (p and q) in order to explore a hard-to-prove assertion
(assert property (r_eq_s)) by reducing the problem to one that can be analyzed successfully.
The variables p and q are large arithmetic expressions, which are typically hard to analyze.
Suppose heuristic knowledge indicates p must be 3, 4 or 5. Then, by adding an assumption for this (i.e., assume property (values_of_p)), the assertion can be proven.
Example 2-7. User-defined Cut Point dut.v
module dut(clk, rst, a, b, c, d, e, f);
input clk, rst;
input [31:0] a,b,c,d,e,f;
wire [31:0] p,q,r,s;
assign p = a * b + (c - d) * (b - f) * (e*f);
assign q = d + e + f + e*e + f*f + a*a;
assign r = (p + 1) + (q - 1) + p;
assign s = 2*p + q;
property r_eq_s;
@(posedge clk) disable iff (rst) r==s;
endproperty
property values_of_p;
@(posedge clk) disable iff (rst) p==3 || p==4 || p==5;
endproperty
assert property (r_eq_s);
assume property (values_of_p);
endmodule本回答被提问者和网友采纳
17-pytest-pytest-assume多重校验
目录
前言
- 当一个用例中有多个断言时,一个断言失败,还想继续执行后面的断言,使用pytest-assume可实现这个需求
安装
- pip install pytest-assume
使用
# -*- coding: utf-8 -*-
# @Time : 2021/10/30
# @Author : 大海
# @File : test_36.py
import pytest
# 断言失败后的不会执行
def test_add():
assert 1 + 1 == 2
assert 1 + 2 == 4
assert 1 + 3 == 4
print('全部执行完成!')
# 断言失败,会继续执行后面的断言
def test_add2():
pytest.assume(1 + 1 == 2)
pytest.assume(1 + 2 == 4)
pytest.assume(1 + 3 == 4)
print('全部执行完成!')
if __name__ == '__main__':
pytest.main(['-s', 'test_36.py'])
以上是关于systemverilog 断言中assume 和assert的区别的主要内容,如果未能解决你的问题,请参考以下文章
如何定义 coverpoint system verilog
pytest文档36-断言失败后还能继续执行pytest-assume