六位数字序列连续出现，输出高电平并报警的verilog语言怎么写？

Posted 2023-03-18

参考技术A 该题目为数电中序列发生器的典型类型，可以使用三段式状态机的方式完成。
假设六位数字序列为100101，则对应代码如下：
module checker(clk,in,rst,out);
/*定义输入，复位，输出信号*/
input clk,in,rst;
output out;
wire clk,in,rst;
reg out;
/*定义并分配状态变量*/
reg [2:0] current_state,next_state;
parameter idle=0,s0=1,s1=2,s2=3,s3=4,s4=5;
/*每次时钟到达，次态赋予现态*/
always@(posedge clk)
begin
if(rst) current_state<=idle;/*同步复位*/
else current_state<=next_state;

end
/*状态转换逻辑*/
always@(current_state or in)
begin
case(current_state)
idle:begin
if(in) next_state<=s0；
else next_state<=idle;
end
s0：begin
if(!in) next_state<=s1；
else next_state<=idle;
end
s1：begin
if(!in) next_state<=s2；
else next_state<=idle;
end
s2：begin
if(in) next_state<=s3；
else next_state<=idle;
end
s3：begin
if(!in) next_state<=s4；
else next_state<=idle;
end
s4：begin
if(in) next_state<=s5；
else next_state<=idle;
end
s5：begin
if(in) next_state<=s0；
else next_state<=idle;
end
default：next_state<=idle;
endcase
end
/*输出逻辑*/
always@(current_state)
begin
if(current_state==s5) out<=1;/*输出报警信号*/
else out<=0;
end
endmodule
望采纳，谢谢！