怎么编写dbutil.java

Posted 2023-04-23

JAVA JDBC工具类代码
packagecom.itfuyun.util;
importjava.sql.DriverManager;
importjava.sql.SQLException;
importjava.sql.Connection;
importjava.sql.PreparedStatement;
importjava.sql.ResultSet;
/**
*
* @author IT浮云 2013-12-3
* [e-mail]
* http://www.itfuyun.com
*/
publicclassDBUtil
privatestaticfinalStringDBDRIVER="com.mysql.jdbc.Driver";//驱动类类名
privatestaticfinalStringDBNAME="app_fuyunjava";//数据库名
privatestaticfinalStringDBURL="jdbc:mysql://localhost:3306/"+DBNAME;//连接URL
privatestaticfinalStringDBUSER="root";//数据库用户名
privatestaticfinalStringDBPASSWORD="root";//数据库密码
privatestaticConnectionconn=null;
privatestaticPreparedStatementps=null;
privatestaticResultSetrs=null;

//获取数据库连接
publicstaticConnectiongetConnection()

try
Class.forName(DBDRIVER);//注册驱动
conn=DriverManager.getConnection(DBURL,DBUSER,DBPASSWORD);//获得连接对象
catch(ClassNotFoundExceptione)//捕获驱动类无法找到异常
e.printStackTrace();
catch(SQLExceptione)//捕获SQL异常
e.printStackTrace();

returnconn;


//查询数据
publicResultSetselect(Stringsql)throwsException
try
conn=getConnection();
ps=conn.prepareStatement(sql);
rs=ps.executeQuery(sql);
returnrs;
catch(SQLExceptionsqle)
thrownewSQLException("select data Exception: "+sqle.getMessage());
catch(Exceptione)
thrownewException("System error: "+e.getMessage());



//插入数据
publicintinsert(Stringsql)throwsException
intnum=0;//计数
try
conn=getConnection();
ps=conn.prepareStatement(sql);
num=ps.executeUpdate();

catch(SQLExceptionsqle)
thrownewSQLException("insert data Exception: "+sqle.getMessage());
finally
try
if(ps!=null)
ps.close();

catch(Exceptione)
thrownewException("ps close exception: "+e.getMessage());

try
if(conn!=null)
conn.close();

catch(Exceptione)
thrownewException("conn close exception: "+e.getMessage());


returnnum;


//删除数据
publicintdelete(Stringsql)throwsException
intnum=0;//计数
try
conn=getConnection();
ps=conn.prepareStatement(sql);
num=ps.executeUpdate();

catch(SQLExceptionsqle)
thrownewSQLException("delete data Exception: "+sqle.getMessage());
finally
try
if(ps!=null)
ps.close();

catch(Exceptione)
thrownewException("ps close Exception: "+e.getMessage());

try
if(conn!=null)
conn.close();

catch(Exceptione)
thrownewException("conn close Exception: "+e.getMessage());


returnnum;


//修改数据
publicintupdate(Stringsql)throwsException
intnum=0;//计数
try
conn=getConnection();
ps=conn.prepareStatement(sql);
num=ps.executeUpdate();
catch(SQLExceptionsqle)
thrownewSQLException("update data Exception: "+sqle.getMessage());
finally
try
if(ps!=null)
ps.close();

catch(Exceptione)
thrownewException("ps close Exception: "+e.getMessage());

try
if(conn!=null)
conn.close();

catch(Exceptione)
thrownewException("conn close Excepiton: "+e.getMessage());


returnnum;

参考技术A 要完成什么功能要求呢

~
~
~
~

请问verilog编写的PWM的死区怎么编写？

参考技术A 很坚定，编写俩个输出PWM1，PWM2,他们之间是几何对称关系。。。。。。这样他们就有一定的死区了，功率放大器CMOS不完全导通 参考技术B 首先要清楚死区是怎么回事，避免驱动器上、下桥臂直通才是问题的本质。 参考技术C 用Verilog实现的PWM硬件。
//-----------------------------32 bits pwm controller------------------------//
//the width is negative
module pwm(clk,write_data,cs,write_n,addr,clr_n,read_data,pwm_out);
//----------------------define the inout put-------------------------//
input clk,cs,clr_n;
input addr;
input write_n;
output pwm_out;
output [31:0] read_data;
input [31:0] write_data;
//--------------------define regs and wires--------------------------//
reg [31:0] period;
reg [31:0] pulse_width;
reg [31:0] counter;
reg off;
reg [31:0] read_data;
wire period_en, pulse_width_en; //enable to write
//-------------------------------------------------------------------//
//define the content of period and pulse_width
always @(posedge clk or negedge clr_n)
begin
if (clr_n==0)
begin
period<=32'h 00000000;
pulse_width<=32'h 00000000;
end
else
begin
if (period_en)//write in preiod data
period<=write_data[31:0];
else
period<=period;
if (pulse_width_en)//write in width data
pulse_width<=write_data[31:0];
else
pulse_width<=pulse_width;
end
end
//------------------------------------------------------------------//
//visit the regs
always @(addr or period or pulse_width)
begin
if (addr == 0)
read_data=period;
else
read_data=pulse_width;
end
//-------------------------------------------------------------------//
//the logic to generate pwm
//the period of pwm
always @(posedge clk or negedge clr_n)
begin
if (clr_n==0)
counter<=0;
else
begin
if (counter>=period-1)
counter<=0;
else
counter<=counter+1;
end
end
//-----------------------------------------------------//
//ajust the width of pwm
always @(posedge clk or negedge clr_n)
begin
if (clr_n==0)
off<=0;
else
if (counter>=pulse_width)
off <= 1;
else
if (counter==0)
off<=0;
else
off<=off;
end
assign period_en = cs & !write_n & !addr;
assign pulse_width_en = cs & !write_n & addr;
//PWM output
assign pwm_out=!off;
endmodule