附录B：Standard Delay Format(SDF)(下)
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文章目录
- B.4 映射实例(Mapping Examples)
- 传播延迟(Propagation Delay)
- 输入建立时间(Input Setup Time)
- 输入保持时间(Input Hold Time)
- 输入建立和保持时间(Input Setup and Hold Time)
- 输入恢复时间(Input Recovery Time)
- 输入撤销时间(Input Removal Time)
- 周期(Period)
- 脉宽(Pulse Width)
- 输入偏斜时间(Input Skew Time)
- 无变化的建立时间(No-change Setup Time)
- 无变化的保持时间(No-change Hold Time)
- 端口延迟(Port Delay)
- 网络延迟(Net Delay)
- 互连路径延迟(Interconnect Path Delay)
- 器件延迟(Device Delay)
- B.5 完整语法(Complete Syntax)
- 知乎翻译圣经
B.4 映射实例(Mapping Examples)
以下是将 S D F SDF SDF结构映射到 V H D L VHDL VHDL泛型（generic）和 V e r i l o g H D L Verilog\\ HDL Verilog HDL声明（declaration）的示例。
传播延迟(Propagation Delay)
- 从输入端口 A A A到输出端口 Y Y Y的传播延迟：上升时间为 0.406 0.406 0.406，下降时间为 0.339 0.339 0.339：
// SDF:
(IOPATH A Y (0.406) (0.339))
-- VHDL generic:
tpd_A_Y : VitalDelayType01;
// Verilog HDL specify path:
(A *> Y) = (tplh$A$Y, tphl$A$Y);
- 从输入端口 O E OE OE到输出端口 Y Y Y的传播延迟：上升时间为 0.441 0.441 0.441，下降时间为 0.409 0.409 0.409。最小、标准和最大延迟是相同的：
// SDF:
(IOPATH OE Y (0.441:0.441:0.441) (0.409:0.409:0.409))
-- VHDL generic:
tpd_OE_Y : VitalDelayType01Z;
// Verilog HDL specify path:
(OE *> Y) = (tplh$OE$Y, tphl$OE$Y);
- 从输入端口 S 0 S0 S0到输出端口 Y Y Y的条件传播延迟：
// SDF:
(COND A==0 && B==1 && S1==0
(IOPATH S0 Y (0.062:0.062:0.062) (0.048:0.048:0.048)
)
)
-- VHDL generic:
tpd_S0_Y_A_EQ_0_AN_B_EQ_1_AN_S1_EQ_0 :
VitalDelayType01;
// Verilog HDL specify path:
if ((A == 1'b0) && (B == 1'b1) && (S1 == 1'b0))
(S0 *> Y) = (tplh$S0$Y, tphl$S0$Y);
- 从输入端口 A A A到输出端口 Y Y Y的条件传播延迟：
// SDF:
(COND B == 0
(IOPATH A Y (0.130) (0.098)
)
)
-- VHDL generic:
tpd_A_Y_B_EQ_0 : VitalDelayType01;
// Verilog HDL specify path:
if (B == 1'b0)
(A *> Y) = 0;
- 从输入端口 C K CK CK到输出端口 Q Q Q的传播延迟：
// SDF:
(IOPATH CK Q (0.100:0.100:0.100) (0.118:0.118:0.118))
-- VHDL generic:
tpd_CK_Q : VitalDelayType01;
// Verilog HDL specify path:
(CK *> Q) = (tplh$CK$Q, tphl$CK$Q);
- 从输入端口 A A A到输出端口 Y Y Y的条件传播延迟：
// SDF:
(COND B == 1
(IOPATH A Y (0.062:0.062:0.062) (0.048:0.048:0.048)
)
)
-- VHDL generic:
tpd_A_Y_B_EQ_1 : VitalDelayType01;
// Verilog HDL specify path:
if (B == 1'b1)
(A *> Y) = (tplh$A$Y, tphl$A$Y);
- 从输入端口 C K CK CK到输出端口 E C K ECK ECK的传播延迟：
// SDF:
(IOPATH CK ECK (0.097:0.097:0.097))
-- VHDL generic:
tpd_CK_ECK : VitalDelayType01;
// Verilog HDL specify path:
(CK *> ECK) = (tplh$CK$ECK, tphl$CK$ECK);
- 从输入端口 C I CI CI到输出端口 S S S的条件传播延迟：
// SDF:
(COND (A == 0 && B == 0) || (A == 1 && B == 1)
(IOPATH CI S (0.511) (0.389)
)
)
-- VHDL generic:
tpd_CI_S_OP_A_EQ_0_AN_B_EQ_0_CP_OR_OP_A_EQ_1_AN_B_EQ_1_CP:
VitalDelayType01;
// Verilog HDL specify path:
if ((A == 1'b0 && B == 1'b0) || (A == 1'b1 && B == 1'b1))
(CI *> S) = (tplh$CI$S, tphl$CI$S);
- 从输入端口 C S CS CS到输出端口 S S S的条件传播延迟：
// SDF:
(COND (A == 1 ^ B == 1 ^ CI1 == 1) &&
!(A == 1 ^ B == 1 ^ CI0 == 1)
(IOPATH CS S (0.110) (0.120) (0.120)
(0.110) (0.119) (0.120)
)
)
-- VHDL generic:
tpd_CS_S_OP_A_EQ_1_XOB_B_EQ_1_XOB_CI1_EQ_1_CP_AN_NT_
OP_A_EQ_1_XOB_B_EQ_1_XOB_CI0_EQ_1_CP:
VitalDelayType01;
// Verilog HDL specify path:
if ((A == 1'b1 ^ B == 1'b1 ^ CI1N == 1'b0) &&
!(A == 1'b1 ^ B == 1'b1 ^ CI0N == 1'b0))
(CS *> S) = (tplh$CS$S, tphl$CS$S);
- 从输入端口 A A A到输出端口 I C O ICO ICO的条件传播延迟：
// SDF:
(COND B == 1 (IOPATH A ICO (0.690)))
-- VHDL generic:
tpd_A_ICO_B_EQ_1 : VitalDelayType01;
// Verilog HDL specify path:
if (B == 1'b1)
(A *> ICO) = (tplh$A$ICO, tphl$A$ICO);
- 从输入端口 A A A到输出端口 C O CO CO的条件传播延迟：
// SDF:
(COND (B == 1 ^ C == 1) && (D == 1 ^ ICI == 1)
(IOPATH A CO (0.263)
)
)
-- VHDL generic:
tpd_A_CO_OP_B_EQ_1_XOB_C_EQ_1_CP_AN_OP_D_EQ_1_XOB_ICI_E
Q_1_CP: VitalDelayType01;
// Verilog HDL specify path:
if ((B == 1'b1 ^ C == 1'b1) && (D == 1'b1 ^ ICI == 1'b1))
(A *> CO) = (tplh$A$CO, tphl$A$CO);
- 从 C K CK CK的上升沿到 Q Q Q的延迟：
// SDF:
(IOPATH (posedge CK) Q (0.410:0.410:0.410)
(0.290:0.290:0.290))
-- VHDL generic:
tpd_CK_Q_posedge_noedge : VitalDelayType01;
// Verilog HDL specify path:
(posedge CK *> Q) = (tplh$CK$Q, tphl$CK$Q);
输入建立时间(Input Setup Time)
- D D D的上升沿与 C K CK CK的上升沿之间的建立时间：
// SDF:
(SETUP (posedge D) (posedge CK) (0.157:0.157:0.157))
-- VHDL generic:
tsetup_D_CK_posedge_posedge: VitalDelayType;
// Verilog HDL timing check task:
$setup(posedge CK, posedge D, tsetup$D$CK, notifier);
- D D D的下降沿与 C K CK CK的上升沿之间的建立时间：
// SDF:
(SETUP (negedge D) (posedge CK) (0.240))
-- VHDL generic:
tsetup_D_CK_negedge_posedge: VitalDelayType;
// Verilog HDL timing check task:
$setup(posedge CK, negedge D, tsetup$D$CK, notifier);
- 输入端口 E E E的上升沿与参考 C K CK CK的上升沿之间的建立时间：
// SDF:
(SETUP (posedge E) (posedge CK) (-0.043:-0.043:-0.043))
-- VHDL generic:
tsetup_E_CK_posedge_posedge : VitalDelayType;
// Verilog HDL timing check task:
$setup(posedge CK, posedge E, tsetup$E$CK, notifier);
- 输入端口 E E E的下降沿和参考 C K CK CK的上升沿之间的建立时间：
// SDF:
(SETUP (negedge E) (posedge CK) (0.101) (0.098))
-- VHDL generic:
tsetup_E_CK_negedge_posedge : VitalDelayType;
// Verilog HDL timing check task:
$setup(posedge CK, negedge E, tsetup$E$CK, notifier);
- S E SE SE和 C K CK CK之间的条件建立时间：
// SDF:
(SETUP (cond E != 1 SE) (posedge CK) (0.155) (0.135))
-- VHDL generic:
tsetup_SE_CK_E_NE_1_noedge_posedge : VitalDelayType;
// Verilog HDL timing check task:
$setup(posedge CK &&& (E != 1'b1), SE, tsetup$SE$CK,
notifier);
输入保持时间(Input Hold Time)
- D D D的上升沿与 C K CK CK的上升沿之间的保持时间：
// SDF:
(HOLD (posedge D) (posedge CK) (-0.166:-0.166:-0.166))
-- VHDL generic:
thold_D_CK_posedge_posedge: VitalDelayType;
// Verilog HDL timing check task:
$hold (posedge CK, posedge D, thold$D$CK, notifier);
- R N RN RN与 S N SN SN之间的保持时间：
// SDF:
(HOLD (posedge RN) (posedge SN) (-0.261:-0.261:-0.261))
-- VHDL generic:
thold_RN_SN_posedge_posedge: VitalDelayType;
// Verilog HDL timing check task:
$hold (posedge SN, posedge RN, thold$RN$SN, notifier);
- 输入端口 S I SI SI与参考端口 C K CK CK之间的保持时间：
// SDF:
(HOLD (negedge SI) (posedge CK) (-0.110:-0.110:-0.110))
-- VHDL generic:
thold_SI_CK_negedge_posedge: VitalDelayType;
// Verilog HDL timing check task:
$hold (posedge CK, negedge SI, thold$SI$CK, notifier);
- E E E和 C K CK CK上升沿之间的条件保持时间：
// SDF:
(HOLD (COND SE ^ RN == 0 E) (posedge CK))
-- VHDL generic:
thold_E_CK_SE_XOB_RN_EQ_0_noedge_posedge:
VitalDelayType;
// Verilog HDL timing check task:
$hold (posedge CK &&& (SE ^ RN == 0), posedge E,
thold$E$CK, NOTIFIER);
输入建立和保持时间(Input Setup and Hold Time)
- 在 D D D和 C L K CLK CLK之间的建立时间与保持时间检查。这是一个有条件的检查，第一个延迟值是建立时间，第二个延迟值是保持时间：
// SDF:
(SETUPHOLD (COND SE ^ RN == 0 D) (posedge CLK)
(0.69) (0.32))
-- VHDL generic (split up into separate setup and hold):
tsetup_D_CK_SE_XOB_RN_EQ_0_noedge_posedge:
VitalDelayType;
thold_D_CK_SE_XOB_RN_EQ_0_noedge_posedge:
VitalDelayType;
-- Verilog HDL timing check (it can either be split up or
-- kept as one construct depending on what appears in the
-- Verilog HDL model):
$setuphold(posedge CK &&& (SE ^ RN == 1'b0)), posedge D,
tsetup$D$CK, thold$D$CK, notifier);
-- Or as:
输入恢复时间(Input Recovery Time)
- C L K A CLKA CLKA和 C L K B CLKB CLKB之间的恢复时间：
// SDF:
(RECOVERY (posedge CLKA) (posedge CLKB)
(1.119:1.119:1.119))
-- VHDL generic:
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