《Static Timing Analysis for Nanometer Designs》汇总传送门

Posted 2023-01-14 KuoGavin

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文章目录

以下是目录索引：

第一章绪论

1.1 静态时序分析是什么(What is Static Timing Analysis)
1.2 数字设计流程(Design Flow)
1.2.1 CMOS数字设计(CMOS Digital Designs)
      1.2.2 FPGA设计(FPGA Designs)
      1.2.3 异步设计(Asynchronous Designs)
1.3 不同阶段的静态时序分析(STA at Different Design Phases)
1.4 STA的局限性(Limitations of Static Timing Analysis)
1.5 其他考虑
      1.5.1 功耗(Power)考虑(Power Considerations)
      1.5.2 可靠性考虑(Reliability Considerations)
1.6 章节概述(Outline of the Book)
相关知识

第二章 STA相关概念

2.1 CMOS逻辑设计(CMOS Logic Design)
      2.1.1 基本MOS结构(Basic MOS Structure)
      2.1.2 CMOS逻辑门(CMOS Logic Gate)
      2.1.3 标准单元(Standard Cells)
2.2 CMOS单元建模(Modeling of CMOS Cells)
2.3 电平切换波形(Switching Waveform)
2.4 传播延时(Propagation Delay)
2.5 波形的压摆(Slew of a Waveform)
2.6 信号偏斜(Skew between Signals)
2.7 时序弧(Timing Arcs and Unateness)
2.8 最小与最大时序路径(Min and Max Timing Paths)
2.9 时钟域(Clock Domains)
2.10 工作条件(Operating Condition)
相关术语

第三章标准单元库(上)

3.1 引脚电容(Pin Capacitance)
3.2 时序模型(Timing Modeling)
      3.2.1 线性时序模型(Linear Timing Model)
      3.2.2 非线性时序模型(Non-linear Timing Model)
      3.2.3 阈值规格和压摆降额(Threshold Specifications and Slew Derating)
3.3 时序模型-组合逻辑单元(Timing Model-Combinational Logic Cells)
      3.3.1 时延和压摆模型(Delay and Slew Models)
      3.3.2 通用组合逻辑块(General Combinational Block)
3.4 时序模型-序列逻辑单元(Timing Models-Sequential Cells)
      3.4.1 同步检查：建立和保持(Synchronous Check: Setup and Hold)
      3.4.2 异步时序检查(Asynchronous Checks)
      3.4.3 传播时延(Propagation Delay)

第三章标准单元库(下)

3.5 状态相关时序模型(state-dependent models)
3.6 黑盒接口时序模型(interface timing model for a black box)
3.7 高级时序建模(advanced timing modeling)
      3.7.1 接收引脚电容(receiver pin capacitance)
      3.7.2 输出电流(output current)
      3.7.3 串扰噪声分析(models for crosstalk noise analysis)
      3.7.4 其它噪声模型(other noise models)
3.8 功耗建模(power dissipation modeling)
      3.8.1 有功功率(active power)
      3.8.2 漏电功率(leakage power)
3.9 单元库中的其它属性(other attributes in cell library)
3.10 特征和工作条件(characterization and operating conditions)
      3.10.1 使用K-系数降额(derating using K-factors)
      3.10.2 库中各单位(library units)

第四章互联寄生

4.1 互连RLC(RLC for Interconnect)
4.2 线负载模型(Wireload Models)
      4.2.1 互连树(Interconnect Trees)
      4.2.2 指定线负载模型(Specifying Wireload Models)
4.3 提取寄生参数的表示方法(Representation of Extracted Parasitics)
      4.3.1 详尽的寄生参数格式(Detailed Standard Parasitics Format)
      4.3.2 精简的寄生参数格式(Reduced Standard Parasitic Format)
      4.3.3 标准的寄生参数格式(Standard Parasitic Extraction Format)
4.4 耦合电容表示方法(Representing Coupling Capacitances)
4.5 分层方法(Hierarchical Methodology)
4.6 减少关键网络的寄生参数(Reducing Parasitics for Critical Nets)

第五章延迟计算

5.1 概述(Overview)
      5.1.1 延迟计算基础(Delay Calculation Basics)
      5.1.2 带互连线的延迟计算(Delay Calculation with Interconnect)
5.2 使用有效电容的单元延迟(Cell Delay using Effective Capacitance)
5.3 互连延迟(Interconnect Delay)
5.4 压摆合并(Slew Merging)
5.5 不同压摆阈值(Different Slew Thresholds)
5.6 不同电压域(Different Voltage Domains)
5.7 路径延迟计算(Path Delay Calculation)
      5.7.1 组合逻辑路径延迟(Combinational Path Delay)
      5.7.2 寄存器路径(Path to a Flip-flop)
      5.7.3 多路径(Multiple Paths)
5.8 裕量计算(Slack Calculation)

第六章串扰和噪声

6.1 概述(Overview)
6.2 串扰毛刺分析(Crosstalk Glitch Analysis)
      6.2.1 基础(Basics)
      6.2.2 毛刺类型(Types of Glitches)
      6.2.3 毛刺阈值和传播(Glitch Thresholds and Propagation)
      6.2.4 多攻击者的噪声累积(Noise Accumulation with Multiple Aggressors)
      6.2.5 攻击者时序相关性(Aggressor Timing Correlation)
      6.2.6 攻击者功能相关性(Aggressor Functional Correlation)
6.3 串扰时延分析(Crosstalk Delay Analysis)
      6.3.1 基础(Basics)
      6.3.2 正负串扰(Positive and Negative Crosstalk)
      6.3.3 多攻击者的累计效应(Accumulation with Multiple Aggressors)
      6.3.4 攻击者与受害者网络的时序相关性(Aggressor Victim Timing Correlation)
      6.3.5 攻击者与受害者网络的功能相关性(Aggressor Victim Functional Correlation)
6.4 使用串扰延迟进行时序检查(Timing Verification Using Crosstalk Delay)
      6.4.1 建立时间分析(Setup Analysis)
      6.4.2 保持时间分析(Holdup Analysis)
6.5 计算复杂度(Computational Complexity)
6.6 噪声避免技术(Noise Avoidance Techniques)

第七章配置STA环境(上)

7.1 什么是STA环境(What is the STA Environment)
7.2 指定时钟(Specifying Clocks)
      7.2.1 时钟不确定度(Clock Uncertainty)
      7.2.2 时钟延迟(Clock Latency)
7.3 衍生时钟(Generated Clocks)
      时钟门控单元输出端的主时钟示例(Example of Master Clock at Clock Gating Cell Output)
      使用Edge和Edge_shift选项生成时钟(Generated Clock using Edge and Edge_shift Options)
      使用Invert选项生成衍生时钟(Generated Clock using Invert Option)
      衍生时钟的时钟延迟(Clock Latency for Generated Clocks)
      典型时钟生成方案(Typical Clock Generation Scenario)
7.4 约束输入路径(Constraining Input Paths)
7.5 约束输出路径(Constraining Output Paths)

第七章配置STA环境(下)

7.6 时序路径组(Timing Path Groups)
7.7 外部属性建模(Modeling of External Attributes)
      7.7.1 驱动强度建模(Modeling Drive Strengths)
      7.7.2 电容负载建模(Modeling Capacitive Load)
7.8 设计规则检查(Design Rule Checks)
7.9 虚拟时钟(Virtual Clocks)
7.10 完善时序分析(Refining the Timing Analysis)
      7.10.1 指定无效信号(Specifying Inactive Signals)
      7.10.2 断开单元中的时序弧(Breaking Timing Arcs in Cells)
7.11 点对点约束(Point-to-Point Specification)
7.12 路径分割(Path Segmentation)

第八章时序检查(上)

8.1 建立时间检查(Setup Timing Check)
      8.1.1 触发器到触发器路径(Flip-flop to Flip-flop Path)
      8.1.2 输入到寄存器路径(Input to Flip-flop Path)
      8.1.3 触发器到输出路径(Flip-flop to Output Path)
      8.1.4 输入到输出路径(Input to Output Path)
      8.1.5 频率直方图(Frequency Histogram)
8.2 保持时间检查(Hold Timing Check)
      8.2.1 触发器到触发器路径(Flip-flop to Flip-flop Path)
      8.2.2 输入到触发器路径(Input to Flip-flop Path)
      8.2.3 触发器到输出路径(Flip-flop to Output Path)
      8.2.4 输入到输出路径(Input to Output Path)

第八章时序检查(中)

8.3 多周期路径(Multicycle Paths)
8.4 伪路径(False Paths)
8.5 半周期路径(Half-Cycle Paths)
8.6 撤销时间检查(Removal Timing Check)
8.7 恢复时间检查(Recovery Timing Check)
8.8 跨时钟域时序(Timing across Clock Domains)
8.8.1 慢速时钟域到快速时钟域(Slow to Fast Clock Domains)
8.8.2 快速时钟域到慢速时钟域(Fast to Slow Clock Domains)

第八章时序检查(下)

8.9 案例(Examples)
      半周期路径(Half-cycle Path)
      快速时钟域到慢速时钟域(Fast to Slow Clock Domain)
      慢速时钟域到快速时钟域(Slow to Fast Clock Domain)
8.10 多时钟(Multiple Clocks)
      8.10.1 整数倍(Integer Multiples)
      8.10.2 非整数倍(Non-Integer Multiples)
      8.10.3 移相(Phase Shifted)

第九章接口分析(上)

9.1 IO接口(IO Interfaces)
      9.1.1 输入接口(Input Interface)
      9.1.2 输出接口(Output Interface)
      9.1.3 时序窗口内的输出变化(Output Change within Window)
9.2 SRAM接口(SRAM Interface)

第九章接口分析(下)

9.3 DDR SDRAM接口(DDR SDRAM Interface)
9.3.1 读周期(Read Cycle)
9.3.2 写周期(Write Cycle)
9.4 DAC接口(Interface to a Video DAC)

第十章鲁棒性检查(上)

10.1 片上变化(On-Chip Variations)
      最差PVT条件下的OCV分析(Analysis with OCV at Worst PVT Condition)
      保持时间检查的OCV(OCV for Hold Checks)
10.2 时间借用(Time Borrowing)
      无借用时间(Example with No Time Borrowed)
      借用时间(Example with Time Borrowed)
      时序违例(Example with Timing Violation)
10.3 数据引脚到数据引脚检查(Data to Data Checks)
10.4 非时序检查(Non-Sequential Check)

第十章鲁棒性检查(中)

10.5 时钟门控检查(Clock Gating Checks)
      高电平时钟门控(Active-High Clock Gating)
      低电平时钟门控(Active-Low Clock Gating)
      使用多路复用器的时钟门控(Clock Gating with a Multiplexer)
      带有时钟反相的时钟门控检查(Clock Gating with Clock Inversion)
10.6 功耗管理(Power Management)
      10.6.1 时钟门控(Clock Gating)
      10.6.2 电源门控(Power Gating)
      10.6.3 多阈值单元(Multi Vt Cells)
      10.6.4 阱极偏置(Well Bias)
10.7 反标(Backannotation)
      10.7.1 SPEF(Standard Parasites Extraction Format)
      10.7.2 SDF(Standard Delay Format)
10.8 签发方法学(Sign-off Methodology)
      互联寄生角(Parasitic Interconnect Corners)
      操作模式(Operating Modes)
      PVT工艺角(PVT Corners)
      多模式多角分析(Multi-Mode Multi-Corner Analysis)

第十章鲁棒性检查(下)

10.9 统计静态时序分析(Statistical Static Timing Analysis)
      10.9.1 工艺和互连走线变化(Process and Interconnect Variations)
      10.9.2 统计分析(Statistics Analysis)
10.10 时序违例路径(Paths Failing Timing)
      路径找不到(No Path Found)
      跨时钟域(Clock Crossing Domain)
      反相衍生时钟(Inverted Generated Clocks)
      缺少虚拟时钟延迟(Missing Virtual Clock Latency)
      IO延迟大(Large IO Delay)
      IO缓冲器延迟不正确(Incorrect IO Buffer Delay)
      延迟值不正确(Incorrect Latency Numbers)
      半周期路径(Half-cycle Path)
      较大的延迟和过渡时间(Large Delays and Transition Times)
      缺少多周期保持时间约束(Missing Multicycle Hold)
      未优化的路径(Path Not Optimized)
      仍不满足时序的路径(Path Still Not Meeting Timing)
      如果仍然不满足时序怎么办(What if Timing Still Cannot be Met)
10.11 验证时序约束
      检查路径例外(Checking Path Exception)
      检查跨时钟域(Checking Clock Domain Crossing)
      验证IO和时钟约束(Validating IO and Clock Constraints)

附录A：Synopsys Design Constraints(SDC)

A.1 基本命令(Basic Commands)
A.2 对象访问命令(Object Access Commands)
A.3 时序约束(Timing Constraints)
A.4 环境命令(Environment Commands)
A.5 多电压命令(Multi-Voltage Commands)

附录B：Standard Delay Format(SDF)(上)

B.1 什么是SDF(What is it)
B.2 SDF格式(The Format)
      B.2.1 例子(Examples)
B.3 标注过程(The Annotation Process)
      B.3.1 Verilog HDL
      B.3.2 VHDL

附录B：Standard Delay Format(SDF)(下)

B.4 映射实例(Mapping Examples)
      传播延迟(Propagation Delay)
      输入建立时间(Input Setup Time)
      输入保持时间(Input Hold Time)
      输入建立和保持时间(Input Setup and Hold Time)
      输入恢复时间(Input Recovery Time)
      输入撤销时间(Input Removal Time)
      周期(Period)
      脉宽(Pulse Width)
      输入偏斜时间(Input Skew Time)
      无变化的建立时间(No-change Setup Time)
      无变化的保持时间(No-change Hold Time)
      端口延迟(Port Delay)
      网络延迟(Net Delay)
      互连路径延迟(Interconnect Path Delay)
      器件延迟(Device Delay)
B.5 完整语法(Complete Syntax)

附录C：Standard Parasitic Extraction Format(SPEF)

C.1 基础(Basics)
C.2 格式(Format)
C.3 完整语法

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