DSP篇--C6678功能调试系列之EDMA3调试

Posted 2022-12-15 nanke_yh

The main blocks of the EDMA3CC are:

• DMA/QDMA Channel Logic: This block consists of logic that captures external system or peripheral events that can be used to initiate event triggered transfers, it also includes registers that allow configuring the DMA/QDMA channels (queue mapping, PaRAM entry mapping). It includes all the registers for different trigger type (manual, external events, chained and auto triggered) for enabling/disabling events, and monitor event status.

• Parameter RAM (PaRAM): Maintains parameter set entries for channel and reload parameter sets. The PaRAM needs to be written with the transfer context for the desired channels and link parameter sets.

• Event queues: These form the interface between the event detection logic and the transfer request submission logic.

• Transfer Request Submission Logic: This logic processes PaRAM sets based on a trigger event submitted to the event queue and submits a transfer request (TR) to the transfer controller associated with the event queue.

• EDMA3 event and interrupt processing registers: Allows mapping of events to parameter sets, enable/disable events, enable/disable interrupt conditions, and clearing interrupts.

• Completion detection: This block detects completion of transfers by the EDMA3TC and/or slave peripherals. Completion of transfers can optionally be used to chain trigger new transfers or to assert interrupts. The logic includes the interrupt processing registers for enabling/disabling interrupt (to be sent to the DSP), interrupt status/clearing registers.

• Memory protection registers: Memory protection registers define the accesses (privilege level and requestor(s)) that are allowed to access the DMA channel shadow region view(s) and regions of PaRAM.

         EDMA主要用于数据的搬运，发送、接收，其搬运数据的形式有；AB模式，ABC模式以及ping-pong模式。

uiCC =  CC_channel>>16;
uiChannel = CC_channel&0xFF;
EDMACCRegs= gpEDMA_CC_regs[uiCC];
/*clear PaRAM*/
PaRAM= (unsigned int *)&(EDMACCRegs->PARAMSET[uiChannel]);
gudEdmaDest = dst;//给全局变量赋值，后续直接引用

if(uiChannel<32)

	//TPCC_ESR= &EDMACCRegs->TPCC_ESR; //Event set register
	//TPCC_IPR= &EDMACCRegs->TPCC_IPR; //Interrupt Pending register
	TPCC_ICR= &EDMACCRegs->TPCC_ICR; //Interrupt Clear Register
	TPCC_EESR= &EDMACCRegs->TPCC_EESR; //Event Enable set register

	TPCC_ECR= &EDMACCRegs->TPCC_ECR; //Event Clear Register
	TPCC_SECR= &EDMACCRegs->TPCC_SECR; //Secondary Event Clear Register
	TPCC_EMCR= &EDMACCRegs->TPCC_EMCR; //Event Missed Clear Register

	//TPCC_EECR = &EDMACCRegs->TPCC_EECR; //Event Enable Clear Register
	uiChannelShift= uiChannel;

else

	//TPCC_ESR= &EDMACCRegs->TPCC_ESRH;
	//TPCC_IPR= &EDMACCRegs->TPCC_IPRH;
	TPCC_ICR= &EDMACCRegs->TPCC_ICRH;
	TPCC_EESR= &EDMACCRegs->TPCC_EESRH;

	TPCC_ECR= &EDMACCRegs->TPCC_ECRH;
	TPCC_SECR= &EDMACCRegs->TPCC_SECRH;
	TPCC_EMCR= &EDMACCRegs->TPCC_EMCRH;

	//TPCC_EECR = &EDMACCRegs->TPCC_EECRH;
	uiChannelShift= uiChannel - 32;


EDMA_channel_TC_cfg(uiCC,uiChannel,uiTC);
EDMA_interrupt_enable(uiCC, uiChannel);

//clear completion flag //clear potential event, status or error
(*TPCC_ICR)=(1<<uiChannelShift);
//clear potential event, status or error
(*TPCC_ECR)=(1<<uiChannelShift);
(*TPCC_SECR)=(1<<uiChannelShift);
(*TPCC_EMCR)=(1<<uiChannelShift);

EDMACCRegs->PARAMSET[uiChannel].OPT=
	CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS,
		CSL_EDMA3_TCCH_DIS,
		CSL_EDMA3_ITCINT_EN,//CSL_EDMA3_ITCINT_DIS  单次传输中断使能
		CSL_EDMA3_TCINT_EN,//CSL_EDMA3_TCINT_DIS 传输完成 中断使能
		uiChannel,
		CSL_EDMA3_TCC_NORMAL,
		CSL_EDMA3_FIFOWIDTH_NONE,
		CSL_EDMA3_STATIC_DIS,
		CSL_EDMA3_SYNC_AB,
		CSL_EDMA3_ADDRMODE_INCR,
		CSL_EDMA3_ADDRMODE_INCR);
EDMACCRegs->PARAMSET[uiChannel].SRC= src;
EDMACCRegs->PARAMSET[uiChannel].A_B_CNT=CSL_EDMA3_CNT_MAKE(uiACount, uiBCount);
EDMACCRegs->PARAMSET[uiChannel].DST=dst;
EDMACCRegs->PARAMSET[uiChannel].SRC_DST_BIDX=CSL_EDMA3_BIDX_MAKE(0,uiACount);
EDMACCRegs->PARAMSET[uiChannel].LINK_BCNTRLD=CSL_EDMA3_LINKBCNTRLD_MAKE(PaRAM, uiBCount);//PaRAM1 0XFFFF
EDMACCRegs->PARAMSET[uiChannel].SRC_DST_CIDX=CSL_EDMA3_CIDX_MAKE((0),(uiACount*uiBCount));/*uiACount*uiBCount不能大于32767*/
EDMACCRegs->PARAMSET[uiChannel].CCNT= uiCCount;
/*ESR手动触发EDMA传输数据*/
//(*TPCC_ESR)= 1<<(uiChannelShift);
/* EESR外部事件(gpio)触发EDMA传输数据*/
(*TPCC_EESR)= 1<<(uiChannelShift);

        EDMA3分初始化、参数配置、以及中断配置。其中中断配置则需要注意的内容主要有：挂载的TC通道，对应的触发事件，以及中断的使能。

Event queues are a part of the EDMA3 channel controller. Event queues form the interface between the event detection logic in the EDMA3CC and the transfer request (TR) submission logic of the EDMA3CC.Each queue is 16 entries deep; thus, each event queue can queue a maximum of 16 events. If there are more than 16 events, then the events that cannot find a place in the event queue remain set in the associated event register and the DSP does not stall.

 The number of event queues in the EDMA3CC determines the number of transfer controllers connected to the EDMA3CC. By default, there is a one-to-one mapping between the queues and transfer controllers. Therefore, the transfer requests (TRs) associated with events in Q0 get submitted to TC0. Similarly,transfer requests associated with events in Q1 get submitted to TC1, and so on.