Format of the CPSR and SPSRs(ARMv7)

Posted 2021-05-14 WangYangkai

Format of the CPSR and SPSRs(ARMv7)

ARM v7-A and ARM v7-R

Reference:
ARM ® Architecture Reference Manual(ARM ® v7-A and ARM ® v7-R edition)

Application Level Programmers’ Model
B1.3 ARM processor modes and core registers
B1.3.3 Program Status Registers (SPSRs)

The format of the CPSR and SPSRs is:

|31|30|29|28|27| 26_25    |24| 23_24_22_21_20    | 19_18_17_16  | 15_14_13_12_11_10  | 9| 8| 7| 6| 5| 4_3_2_1_0     |
|_N|_Z|_C|_V|_Q|_,_IT[1:0]|_J|_,_,_,_,_[reserved]|_,_,_,_GE[3:0]|_,_,_,_,_,_,_IT[7:2]|_E|_A|_I|_F|_T|_,_,_,_,_M[4:0]|


Condition code flags, bits [31:28] 
    Set on the result of instruction execution. The flags are:
    N, bit [31]  Negative condition code flag
    Z, bit [30]  Zero condition code flag
    C, bit [29]  Carry condition code flag
    V, bit [28]  Overflow condition code flag.



Q, bit [27]  Cumulative saturation flag. This flag can be read or written in any mode, and is described in The Application Program Status Register (APSR) on page A2-14.



IT[7:0], bits [15:10,26:25] 
If-Then execution state bits for the Thumb IT (If-Then) instruction.



J, bit [24]  Jazelle bit, see the description of the T bit, bit [5].



Bits [23:20]  Reserved. RAZ/SBZP.


GE[3:0], bits [19:16] 
Greater than or Equal flags, for SIMD instructions.



E, bit [9]  Endianness execution state bit. Controls the load and store endianness for data accesses:
0  Little endian operation
1  Big endian operation.
This bit is ignored by instruction fetches.



Mask bits, bits [8:6] 
The mask bits disable some asynchronous exceptions. The three mask bits are:
A, bit [8]  Asynchronous abort disable bit. Used to mask asynchronous aborts.
I, bit [7]  Interrupt disable bit. Used to mask IRQ interrupts.
F, bit [6]  Fast interrupt disable bit. Used to mask FIQ interrupts.
The possible values of each bit are:
0  Exception enabled
1  Exception disabled.
The mask bits can be written only in privileged modes. Their values can be read in any mode, but use of their values and attempts to change them by User mode code are deprecated.
Updates to the F bit are restricted if Non-maskable Fast Interrupts (NMFIs) are supported, see Non-maskable fast interrupts on page B1-18.
If implemented, the Security Extensions can restrict updates to the A and F bits from the Non-secure state, see Use of the A, F, and Mode bits by the Security Extensions on page B1-19.



T, bit [5]  Thumb execution state bit. This bit and the J execution state bit, bit [24], determine the instruction set state of the processor, ARM, Thumb, Jazelle, or ThumbEE.



M[4:0], bits [4:0] 
Mode field. This field determines the current mode of the processor. The permitted values of this field are listed in Table B1-1 on page B1-6. All other values of M[4:0] are reserved. 

The effect of setting M[4:0] to a reserved value is UNPREDICTABLE.For more information about the processor modes see ARM processor modes on page B1-6. 
Figure B1-1 on page B1-9 shows the registers that can be accessed in each mode.

This field can be written only in privileged modes. Its value can be read in any mode, but use of its value and attempts to change it by User mode code are deprecated. 

If implemented, the Security Extensions restrict use of the mode field to enter Monitor and FIQ modes, see Use of the A, F, and Mode bits by the Security Extensions on page B1-19.

Coding in 2021/05/13

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