Verilog编的8-3编码器

Posted 2023-02-15

以下是我编的8-3编码器。请看下有什么问题吗module decoder(in,out,none_on);
input [7:0]in;
output [2:0]out;
output none_on;
reg [2:0]out;
none_on = 0;
always
begin
case(in)
10000000:
out = 111;
01000000:
out = 110;
00100000:
out = 101;
00010000:
out = 100;
00001000:
out = 011;
00000100:
out = 010;
00000010:
out = 001;
00000001:
out = 000;
default
out = 3'bz;
none_on = 1;
endcase
end
endmodule

你写的代码有如下错误或者不恰当的地方：1. 贴出来的代码没有编排，别人看起来根本没有所谓的coding style，看不了，谁会帮你分析，谁会回答呢？2. none_on的功能不明确，而且声明不正确。因该是reg none_on;不能直接写none_on。module decoder(in,out,none_on);
input [7:0] in;
output [2:0] out;
output none_on;
reg [2:0] out; // code start
always begin
case(in)
10000000: out = 111;
01000000: out = 110;
00100000: out = 101;
00010000: out = 100;
00001000: out = 011;
00000100: out = 010;
00000010: out = 001;
00000001: out = 000;
default: out = 3'b0;
endcase none_on = 1;
end
endmodule 参考技术A 应该是付值写错了,要写成<=