MacOS下也能做Verilog开发/仿真/综合
Posted 硅农
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安装开发环境
/bin/zsh -c "$(curl -fsSL https://gitee.com/cunkai/HomebrewCN/raw/master/Homebrew.sh)"
brew install icarus-verilog
brew install verilator
brew cask install xquartz
brew cask insatll gtkwave
cpan install Switch
perl -V:'installsitelib'
/usr/local/Cellar/perl/...
,则必须将Switch复制到以下位置/Library/Perl/5.*/
:
sudo cp /usr/local/Cellar/perl/5.*/lib/perl5/site_perl/5.*/Switch.pm /Library/Perl/5.*/
/Applications/gtkwave.app/Contents/Resources/bin/gtkwave
~/.bash_profile
alias gtkwave = /Applications/gtkwave.app/Contents/Resources/bin/gtkwave
gtkwave
直接打开gtkwave
source ~/.bash_porfile
才能使用
source ~/.bash_porfile
编译仿真
echo "开始编译"
iverilog -o wave ../src/I2C_Ctrl_EEPROM.v I2C_Ctrl_EEPROM_tb.v
echo "编译完成"
vvp -n wave -lxt2
echo "生成波形文件"
cp wave.vcd wave.lxt
echo "打开波形文件"
gtkwave wave.lxt
source run.sh
,一键仿真跑起来,会打印出如下信息
开始编译
编译完成
LXT2 info: dumpfile wave.vcd opened for output.
生成波形文件
打开波形文件
综合
brew install yosys
module counter (clk, rst, en, count);
input clk, rst, en;
output reg [3:0] count;
always @(posedge clk)
if (rst)
count <= 4'd0;
else if (en)
count <= count + 4'd1;
endmodule
# read design
read_verilog counter.v
hierarchy -top counter
# high-level synthesis
opt; fsm; opt; memory; opt; #techmap; opt;
write_verilog synth.v
yosys show_rtl.ys
brew install graphviz
yosys -p "prep; show -stretch -prefix counter -format dot" counter.v
dot counter.dot -T png -o counter.png
最后
Reference
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