I/O Permission Bit Map in Task State Segment(TSS)

Posted 2021-06-29 rtoax

摘自《Intel® 64 and IA-32 Architectures Software Developer’s Manual Combined Volumes1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D and 4》

Because each task has its own TSS, each task has its own I/O permission bit map. 

If in protected mode and the CPL is less than or equal to the current IOPL, the processor allows all I/O operations to proceed. If the CPL is greater than the IOPL or if the processor is operating in virtual-8086 mode, the processor checks the I/O permission bit map to determine if access to a particular I/O port is allowed. Each bit in the map corresponds to an I/O port byte address. For example, the control bit for I/O port address 29H in the I/O address space is found at bit position 1 of the sixth byte in the bit map. Before granting I/O access, the processor tests all the bits corresponding to the I/O port being addressed. For a doubleword access, for example, the processors tests the four bits corresponding to the four adjacent 8-bit port addresses. If any tested bit is set, a general-protection exception (#GP) is signaled. If all tested bits are clear, the I/O operation is allowed to proceed.