数字电路个人实验二
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代码
module p2s (data_in,clock,reset,load,data_out,done) ;
input [3:0] data_in;
input clock, reset, load;
output data_out;
output done;
reg done;
reg [3:0] temp;
reg [3:0] cnt;
always@ (posedge clock or posedge reset )begin
if (reset)
begin
temp<=0;
cnt<=0;
done<=1;
end
else if(load)
begin
temp<=data_in;
cnt<=0;
done<=0;
end
else if (cnt==3)
begin
temp <={temp[2:0],1'b0};
cnt<=0;
done<=1;
end
else
begin
temp <={temp[2:0],1'b0};
cnt<=cnt+1;
done<=0;
end
end
assign data_out=(done==1)?1 'bz:temp[3];
endmodule
测试文件
module p2s(data_in,clock,reset,load,data_out,done);
input [3:0] data_in;
input clock,reset,load;
output data_out;
output done;
reg done;
reg [3:0] temp;
reg [3:0] cnt;
always@(posedge clock or posedge reset )
begin
if(reset)
begin
temp<=0;
cnt<=0;
done<=1;
end
else if(load)
begin
temp<=data_in;
cnt<=0;
done<=0;
end
else if(cnt==3)
begin
temp <= {temp[2:0],1'b0};
cnt<=0;
done<=1;
end
else
begin
temp <= {temp[2:0],1'b0};
cnt<=cnt+1;
done<=0;
end
end
assign data_out=(done==1)?1'bz:temp[3];
endmodule
module tbp2s;
reg [3:0] data_in;
reg clock,reset,load;
wire data_out;
wire done;
initial
begin
reset=1;
#15 reset=0;
end
initial clock=1;
always #5 clock=~clock;
always @(done)
begin
if(done==1)
begin
data_in=$random%16;
load=1;
end
else
begin
load=0;
end
end
always @(posedge clock)
if(load==1)
begin:dis
integer i;
i=3;
repeat(4)
begin
@(posedge clock)
if(data_out==data_in[i])
$display("Output Right!");
else
$display("Bed Output!data_out= %b ,but data_in[%d]= %b",data_out,i,data_in[i]);
i=i-1;
end
end
p2s ip2s(data_in,clock,reset,load,data_out,done);
endmodule
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