谁能帮我把这个程序改为verilog语言必有重谢

Posted 2023-03-28

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity epm240 is
port(clk :in std_logic; --系统时钟
oe :out std_logic; --TLC5510的输出使能/OE
clk1:out std_logic; --TLC5510的转换时钟
din:in std_logic_vector(7 downto 0); --来自TLC5510的采样数据
dout:out std_logic_vector(7 downto 0);
KEY:in std_logic;
clkout:out std_logic);--FPGA数据输出
end epm240;
architecture behav of epm240 is
signal q:std_logic; --全局变量
begin
led:block
SIGNAL KIN,CLKTMP,T:STD_LOGIC:='1';
begin
process(clk)
VARIABLE m:std_logic_vector(26 downto 0);
begin
if clk'event and clk='1' then
m:=m+1;
end if;
IF T='1' THEN
clkout<=m(26);
--clkout1<=m(24);
ELSE
clkout<=m(24);
--clkout1<=m(26);
END IF;
CLKTMP<=M(19);
end process;
KEYBOARD_DIFF : block
signal D0,D1 : STD_LOGIC:='1';
begin
process (CLKTMP)
begin
if CLKTMP'event and CLKTMP='1' then --CLK rising
D1<=D0; D0<=not KEY; --delay
end if;
end process;
KIN <= D0 and not D1; --differential
end block KEYBOARD_DIFF;
process(KIN)
begin
if KIN'event and KIN='0' then
T<=NOT T;
end if;
end process;
end block led;
process(clk) --此进程中，把CLK 进行4分频，得到TLC5510的转换时钟
begin
if clk'event and clk='1' then
q<=not q;
end if;
clk1<=q; --对系统CLK进行4分频
end process;
oe<='0';
dout<=din; --采样数据输出
end behav;

module epm240(input clk, output oe, output clk1, input [7:0] din, output [7:0] dout, input KEY, output clkout);
reg [26:0] m;
always @(posedge clk) m<=m+27\'b1;
assign clkout = T ? m[26] : m[24];
// assign clkout1 = T ? m[24] : m[26];
assign clktmp = m[19];
reg D0, D1;
always @(posedge CLKTMP) begin
D1 <= D0;
D0 <= ~KEY;
end
assign kin = D0 &~ D1;
reg T, q;
always @(negedge kin) T <= ~T;
always @(posedge clk) q <= ~q;
assign clk1 = q;
assign oe = 0;
assign dout = din;
endmodule
建议你不要大小写混用，代码里面全部用小写，只有宏或者parameter采用大写。 参考技术A 看看书吧，这么长的代码，懒得写了。追问

看样你会吧
依然谢谢

参考技术B 什么重谢啊？