木马FPGA中的木马程序

Posted 2022-04-01 fpga&matlab

`timescale 1 ns / 1 ps 

module MixColumns_Four_Term_Multiplication (
        p_read,
        p_read1,
        p_read2,
        p_read3,
        ap_return_0,
        ap_return_1,
        ap_return_2,
        ap_return_3
);

parameter    ap_true = 1'b1;
parameter    ap_const_lv8_1 = 8'b1;
parameter    ap_const_lv32_7 = 32'b111;
parameter    ap_const_lv8_1B = 8'b11011;
parameter    ap_const_logic_1 = 1'b1;
parameter    ap_const_logic_0 = 1'b0;

input  [7:0] p_read;
input  [7:0] p_read1;
input  [7:0] p_read2;
input  [7:0] p_read3;
output  [7:0] ap_return_0;
output  [7:0] ap_return_1;
output  [7:0] ap_return_2;
output  [7:0] ap_return_3;

wire   [7:0] result_fu_45_p2;
wire   [0:0] tmp_2_fu_51_p3;
wire   [7:0] result_1_fu_59_p2;
wire   [7:0] result_3_fu_73_p2;
wire   [0:0] tmp_4_fu_79_p3;
wire   [7:0] result_4_fu_87_p2;
wire   [7:0] result_2_fu_65_p3;
wire   [7:0] tmp2_fu_107_p2;
wire   [7:0] result_5_fu_93_p3;
wire   [7:0] tmp1_fu_113_p2;
wire   [7:0] tmp_fu_101_p2;
wire   [7:0] result_6_fu_125_p2;
wire   [0:0] tmp_6_fu_131_p3;
wire   [7:0] result_7_fu_139_p2;
wire   [7:0] result_8_fu_145_p3;
wire   [7:0] tmp5_fu_159_p2;
wire   [7:0] tmp4_fu_165_p2;
wire   [7:0] tmp3_fu_153_p2;
wire   [7:0] result_9_fu_177_p2;
wire   [0:0] tmp_8_fu_183_p3;
wire   [7:0] result_10_fu_191_p2;
wire   [7:0] result_11_fu_197_p3;
wire   [7:0] tmp8_fu_211_p2;
wire   [7:0] tmp7_fu_217_p2;
wire   [7:0] tmp6_fu_205_p2;
wire   [7:0] tmp11_fu_235_p2;
wire   [7:0] tmp10_fu_241_p2;
wire   [7:0] tmp9_fu_229_p2;
wire   [7:0] OUT_fu_119_p2;
wire   [7:0] OUT_1_fu_171_p2;
wire   [7:0] OUT_2_fu_223_p2;
wire   [7:0] OUT_3_fu_247_p2;

assign OUT_1_fu_171_p2 = (tmp4_fu_165_p2 ^ tmp3_fu_153_p2);
assign OUT_2_fu_223_p2 = (tmp7_fu_217_p2 ^ tmp6_fu_205_p2);
assign OUT_3_fu_247_p2 = (tmp10_fu_241_p2 ^ tmp9_fu_229_p2);
assign OUT_fu_119_p2 = (tmp1_fu_113_p2 ^ tmp_fu_101_p2);
assign ap_return_0 = OUT_fu_119_p2;
assign ap_return_1 = OUT_1_fu_171_p2;
assign ap_return_2 = OUT_2_fu_223_p2;
assign ap_return_3 = OUT_3_fu_247_p2;
assign result_10_fu_191_p2 = (result_9_fu_177_p2 ^ ap_const_lv8_1B);
assign result_11_fu_197_p3 = ((tmp_8_fu_183_p3[0:0]==1'b1)? result_10_fu_191_p2: result_9_fu_177_p2);
assign result_1_fu_59_p2 = (result_fu_45_p2 ^ ap_const_lv8_1B);
assign result_2_fu_65_p3 = ((tmp_2_fu_51_p3[0:0]==1'b1)? result_1_fu_59_p2: result_fu_45_p2);
assign result_3_fu_73_p2 = p_read1 << ap_const_lv8_1;
assign result_4_fu_87_p2 = (result_3_fu_73_p2 ^ ap_const_lv8_1B);
assign result_5_fu_93_p3 = ((tmp_4_fu_79_p3[0:0]==1'b1)? result_4_fu_87_p2: result_3_fu_73_p2);
assign result_6_fu_125_p2 = p_read2 << ap_const_lv8_1;
assign result_7_fu_139_p2 = (result_6_fu_125_p2 ^ ap_const_lv8_1B);
assign result_8_fu_145_p3 = ((tmp_6_fu_131_p3[0:0]==1'b1)? result_7_fu_139_p2: result_6_fu_125_p2);
assign result_9_fu_177_p2 = p_read3 << ap_const_lv8_1;
assign result_fu_45_p2 = p_read << ap_const_lv8_1;
assign tmp10_fu_241_p2 = (tmp11_fu_235_p2 ^ p_read2);
assign tmp11_fu_235_p2 = (result_11_fu_197_p3 ^ p_read3);
assign tmp1_fu_113_p2 = (tmp2_fu_107_p2 ^ result_5_fu_93_p3);
assign tmp2_fu_107_p2 = (p_read2 ^ p_read3);
assign tmp3_fu_153_p2 = (result_5_fu_93_p3 ^ p_read);
assign tmp4_fu_165_p2 = (tmp5_fu_159_p2 ^ p_read1);
assign tmp5_fu_159_p2 = (result_8_fu_145_p3 ^ p_read3);
assign tmp6_fu_205_p2 = (p_read1 ^ p_read);
assign tmp7_fu_217_p2 = (tmp8_fu_211_p2 ^ result_8_fu_145_p3);
assign tmp8_fu_211_p2 = (result_11_fu_197_p3 ^ p_read2);
assign tmp9_fu_229_p2 = (result_2_fu_65_p3 ^ p_read1);
assign tmp_2_fu_51_p3 = p_read[ap_const_lv32_7];
assign tmp_4_fu_79_p3 = p_read1[ap_const_lv32_7];
assign tmp_6_fu_131_p3 = p_read2[ap_const_lv32_7];
assign tmp_8_fu_183_p3 = p_read3[ap_const_lv32_7];
assign tmp_fu_101_p2 = (result_2_fu_65_p3 ^ p_read);

endmodule //MixColumns_Four_Term_Multiplication

A37-05