请问用if写出四选一多路选择器的vhdl的设计，怎么写？

Posted 2023-04-11

参考技术A library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity sixuanyi is
port(clk:in std_logic;
sel:in std_logic_vector(1 downto 0);
a,b,c,d:out std_logic);
end sixuanyi;

architecture of4 of sixuanyi is

signal aa :std_logic;
signal bb :std_logic;
signal cc :std_logic;
signal dd :std_logic;
begin
process(clk)

begin

if(clk'event and clk='1' and clk'last_value='0')then

if(sel="00")then aa<='1';else aa<='0';
end if;
if(sel="01")then bb<='1';else bb<='0';
end if;
if(sel="10")then cc<='1';else cc<='0';
end if;
if(sel="11")then dd<='1';else dd<='0';
end if;
end if;

a<=aa;
b<=bb;
c<=cc;
d<=dd;
end process;
end of4;本回答被提问者采纳 参考技术B module mux( clk, rst, a,b,c,d,sel,e)
input clk;
input rst;
input a,b,c,d;
input [1:0] sel;
output e;
reg e;
always @(posedge clk or negedge rst)
begin
if (!rst)
e<=1'b0;
else if (sel==2'b00)
e<=a;
else if (sel==2'b01)
e<=b;
else if(sel==2'b10)
e<=c;
else (sel==2'b11)
e<=d;
end
endmodule

如何用ＶＨＤＬ语言设计四位全加器

用ＶＨＤＬ语言设计一个四位全加器．．．会的帮帮忙．．．ＶＨＤＬ语言啊

VHDL语言设计四位全加器：
library IEEE;
use IEEE.Std_logic_1164.ALL;
entity pro1 is
port(A1,B1,G1BAR,A0,B0,G0BAR:in std_logic;
Y20,Y21,Y22,Y23,Y10,Y11,Y12,Y13:out std_logic);
end pro1;

architecture pro1_arch of pro1 is
begin
Y10<=\'0\' when(B0=\'0\') and ((A0=\'0\') and (G0BAR=\'0\')) else \'1\';
Y11<=\'0\' when(B0=\'0\') and ((A0=\'1\') and (G0BAR=\'0\')) else \'1\';
Y12<=\'0\' when(B0=\'1\') and ((A0=\'0\') and (G0BAR=\'0\')) else \'1\';
Y13<=\'0\' when(B0=\'1\') and ((A0=\'1\') and (G0BAR=\'0\')) else \'1\';
Y20<=\'0\' when(B1=\'0\') and ((A1=\'0\') and (G1BAR=\'0\')) else \'1\';
Y21<=\'0\' when(B1=\'0\') and ((A1=\'1\') and (G1BAR=\'0\')) else \'1\';
Y22<=\'0\' when(B1=\'1\') and ((A1=\'0\') and (G1BAR=\'0\')) else \'1\';
Y23<=\'0\' when(B1=\'1\') and ((A1=\'1\') and (G1BAR=\'0\')) else \'1\';
end pro1_arch;

能实现四位二进制数全加的数字电路模块，称之为四位全加器。
http://baike.baidu.com/link?url=GaCnz6D-_GQfu1rs_YfE_cZKiwRMcRtEpeLDS2Nn-0UlA39xIq_E2Vw8ttNptjB-kaKIblYblcLCXucw3cbaIK 参考技术A 设计一个四位的全加器(功能说明见实验二.(二).2) 6.设计一个7位奇偶校验电路(功能说明见实验二.(二).4) 7.数字比较器,设计4位二进制数字比较器 (二)基于VHDL的时序电路设计 用VHDL语言编写实现下列器件功能的程序并进行编译,... 参考技术B library IEEE;
use IEEE.Std_logic_1164.ALL;
entity pro1 is
port(A1,B1,G1BAR,A0,B0,G0BAR:in std_logic;
Y20,Y21,Y22,Y23,Y10,Y11,Y12,Y13:out std_logic);
end pro1;

architecture pro1_arch of pro1 is
begin
Y10<='0' when(B0='0') and ((A0='0') and (G0BAR='0')) else '1';
Y11<='0' when(B0='0') and ((A0='1') and (G0BAR='0')) else '1';
Y12<='0' when(B0='1') and ((A0='0') and (G0BAR='0')) else '1';
Y13<='0' when(B0='1') and ((A0='1') and (G0BAR='0')) else '1';
Y20<='0' when(B1='0') and ((A1='0') and (G1BAR='0')) else '1';
Y21<='0' when(B1='0') and ((A1='1') and (G1BAR='0')) else '1';
Y22<='0' when(B1='1') and ((A1='0') and (G1BAR='0')) else '1';
Y23<='0' when(B1='1') and ((A1='1') and (G1BAR='0')) else '1';
end pro1_arch; 参考技术C library IEEE;
use IEEE.Std_logic_1164.ALL;
entity pro1 is
port(A1,B1,G1BAR,A0,B0,G0BAR:in std_logic;
Y20,Y21,Y22,Y23,Y10,Y11,Y12,Y13:out std_logic);
end pro1;

architecture pro1_arch of pro1 is
begin
Y10<='0' when(B0='0') and ((A0='0') and (G0BAR='0')) else '1';
Y11<='0' when(B0='0') and ((A0='1') and (G0BAR='0')) else '1';
Y12<='0' when(B0='1') and ((A0='0') and (G0BAR='0')) else '1';
Y13<='0' when(B0='1') and ((A0='1') and (G0BAR='0')) else '1';
Y20<='0' when(B1='0') and ((A1='0') and (G1BAR='0')) else '1';
Y21<='0' when(B1='0') and ((A1='1') and (G1BAR='0')) else '1';
Y22<='0' when(B1='1') and ((A1='0') and (G1BAR='0')) else '1';
Y23<='0' when(B1='1') and ((A1='1') and (G1BAR='0')) else '1';
end pro1_arch; 参考技术D library IEEE;
use IEEE.Std_logic_1164.ALL;
entity pro1 is
port(A1,B1,G1BAR,A0,B0,G0BAR:in std_logic;
Y20,Y21,Y22,Y23,Y10,Y11,Y12,Y13:out std_logic);
end pro1;

architecture pro1_arch of pro1 is
begin
Y10<='0' when(B0='0') and ((A0='0') and (G0BAR='0')) else '1';
Y11<='0' when(B0='0') and ((A0='1') and (G0BAR='0')) else '1';
Y12<='0' when(B0='1') and ((A0='0') and (G0BAR='0')) else '1';
Y13<='0' when(B0='1') and ((A0='1') and (G0BAR='0')) else '1';
Y20<='0' when(B1='0') and ((A1='0') and (G1BAR='0')) else '1';
Y21<='0' when(B1='0') and ((A1='1') and (G1BAR='0')) else '1';
Y22<='0' when(B1='1') and ((A1='0') and (G1BAR='0')) else '1';
Y23<='0' when(B1='1') and ((A1='1') and (G1BAR='0')) else '1';
end pro1_arch;