FPGA数码管显示

Posted 2022-11-12 ACheng63201

数码管

• 数码管显示部分的电路如图所示。我们使用的是一个四位带小数点的七段共阳数码管，当我们相应的输出脚为低电平时，该段位的LED点亮。位选位也是低电平选通。

模块实现

//数码管显示
module digitalTube(
    input Clk,//时钟50M
    input Rst_n,//重置
    input En,//使能
    input [15:0] data,//要显示的数据
    output [3:0] sel,//数码管位选
    output reg[7:0]seg//数码管段选
    );
    reg [14:0]divider_cnt;//分频计数器（25000-1）50M/25000/2=1000
	reg clk_1K;//分频时钟
	reg [3:0]data_tmp;//数据缓存
	reg [3:0]sel_r;//数码管循环位选

	//	分频计数器计数模块
	always@(posedge Clk or posedge Rst_n)
        if(Rst_n)
            divider_cnt <= 15'd0;
        else if(!En)
            divider_cnt <= 15'd0;
        else if(divider_cnt == 24999)
            divider_cnt <= 15'd0;
        else
		  divider_cnt <= divider_cnt + 1'b1;
	//1K扫描时钟生成模块		
	always@(posedge Clk or posedge Rst_n)
        if(Rst_n)
            clk_1K <= 1'b0;
        else if(divider_cnt == 24999)
            clk_1K <= ~clk_1K;
        else
            clk_1K <= clk_1K;
    //4位循环移位寄存器,实现数码管的位选
	always@(posedge clk_1K or posedge Rst_n)
	if(Rst_n)
		sel_r <= 4'b1110;
	else
		sel_r <=  sel_r[2:0],sel_r[3];
    //数码管位赋值
    always@(*)
        case(sel_r)
            4'b1110:data_tmp = data[3:0];
            4'b1101:data_tmp = data[7:4];
            4'b1011:data_tmp = data[11:8];
            4'b0111:data_tmp = data[15:12];
            default:data_tmp = 4'b0000;
        endcase
    //数码管显示
    always@(*)
		case(data_tmp)
			4'h0:seg = 8'b00000011;
			4'h1:seg = 8'b10011111;
			4'h2:seg = 8'b00100101;
			4'h3:seg = 8'b00001101;
			4'h4:seg = 8'b10011001;
			4'h5:seg = 8'b01001001;
			4'h6:seg = 8'b01000001;
			4'h7:seg = 8'b00011111;
			4'h8:seg = 8'b00000001;
			4'h9:seg = 8'b00001001;
			4'ha:seg = 8'b00010001;
			4'hb:seg = 8'b11000001;
			4'hc:seg = 8'b01100011;
			4'hd:seg = 8'b10000101;
			4'he:seg = 8'b01100001;
			4'hf:seg = 8'b01110001;
		endcase
    assign sel = (En)?sel_r:4'b1111;
endmodule

仿真结果