[笔记]再笔记--边干边学Verilog HDL –00６

Posted 2022-06-30 mb62bc064f8f791

ｌａｂ０６－－ＳＯＳ信号之二

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如上图所示，本实验在ｌａｂ０５的基础上修改控制部分，使得实验效果更实际，由按键启动ｓｏｓ信号的产生。用到ｌａｂ０４的按键消抖模块和ｌａｂ０５的ｓｏｓ产生模块，本实验添加了一个用于协调的控制模块。

代码

debounce_module2.v

1 /**
 2  * File name : debounce_module2.v
 3  *
 4  */
 5  
 6 module debounce_module2
 7 (
 8     clk, rst_n, pin_in, pin_out
 9 );
10 
11         input clk;
12         input rst_n;
13         input pin_in;
14         output pin_out;
15         
16         wire h2l;
17         wire l2h;
18         
19         detect_module U1
20         (
21             .clk (clk),
22             .rst_n (rst_n),
23             .pin_in (pin_in),
24             .h2l (h2l),
25             .l2h (l2h)
26         );
27 
28         delay_module U2
29         (
30             .clk (clk),
31             .rst_n (rst_n),
32             .h2l (h2l),
33             .l2h (l2h),
34             .pin_out (pin_out)
35         );
36 
37 endmodule
38

1 /**
 2  * File name : detect_module.v
 3  *
 4  */
 5  
 6 module detect_module
 7 (
 8     clk, rst_n, pin_in, h2l, l2h
 9 );
10 
11     input clk;
12     input rst_n;
13     input pin_in;
14     output h2l;
15     output l2h;
16     
17     parameter T100US = 13d5000 -1;
18     
19     reg [12:0] count;
20     reg isen;
21     
22     always @(posedge clk or negedge rst_n)
23         if (!rst_n)
24             begin
25                 count <= 13d0;
26                 isen <= 1b0;
27             end
28         else if (count == T100US)
29             isen <= 1b1;
30         else
31             count <= count + 1b1;
32             
33     reg h2l_f1;
34     reg h2l_f2;
35     reg l2h_f1;
36     reg l2h_f2;
37     
38     always @(posedge clk or negedge rst_n)
39         if (!rst_n)
40             begin
41                 h2l_f1 <= 1b1;
42                 h2l_f2 <= 1b1;
43                 l2h_f1 <= 1b0;
44                 l2h_f2 <= 1b0;
45             end
46         else
47             begin
48                 h2l_f1 <= pin_in;
49                 h2l_f2 <= h2l_f1;
50                 l2h_f1 <= pin_in;
51                 l2h_f2 <= l2h_f1;
52             end
53 
54     assign h2l = isen ? (h2l_f2 & !h2l_f1) : 1b0;
55     assign l2h = isen ? (!l2h_f2 & l2h_f1) : 1b0;
56 
57 endmodule
58     
59

1 /**
 2  * File name: delay_module.v
 3  *
 4  */
 5 
 6 module delay_module
 7 (
 8     clk, rst_n, h2l, l2h, pin_out
 9 );
10 
11     input clk;
12     input rst_n;
13     input h2l;
14     input l2h;
15     output pin_out;
16     
17     parameter T1MS = 16d50000 - 1;
18     
19     reg [15:0] count;
20     
21     always @(posedge clk or negedge rst_n)
22         if (!rst_n)
23             count <= 16d0;
24         else if (iscount && count == T1MS)
25             count <= 16d0;
26         else if (iscount)
27             count <= count + 1b1;
28         else if (!iscount)
29             count <= 16d0;
30             
31     reg [3:0] count_ms;
32 
33     always @(posedge clk or negedge rst_n)
34         if (!rst_n)
35             count_ms <= 4d0;
36         else if (iscount && count == T1MS)
37             count_ms <= count_ms + 1b1;
38         else if (!iscount)
39             count_ms <= 4d0;
40             
41     reg iscount;
42     reg rpin_out;
43     reg [1:0] i;
44     
45     always @(posedge clk or negedge rst_n)
46         if (!rst_n)
47             begin
48                 iscount <= 1b0;
49                 rpin_out <= 1b0;
50                 i <= 2d0;
51             end
52         else
53             case (i)
54             
55                 2d0:
56                 if (h2l) i <= 2d1;
57                 else if (l2h) i <= 2d3;
58                 
59                 2d1:
60                 if (count_ms == 4d10) 
61                     begin
62                         iscount <= 1b0;
63                         rpin_out <= 1b1;
64                         i <= 2d2;
65                     end
66                 else
67                     iscount <= 1b1;
68                     
69                 2d2:
70                 begin
71                     rpin_out <= 1b0;
72                     i <= 2d0;
73                 end
74 
75                 2d3:
76                 if (count_ms == 4d10)
77                     begin
78                         iscount <= 1b0;
79                         i <= 2d0;
80                     end
81                 else
82                     iscount <= 1b1;
83             endcase
84                         
85     assign pin_out = rpin_out;
86 
87 endmodule

inter_control_modul.v

1 /**
 2  * File name : inter_control_module.v
 3  *
 4  */
 5 
 6 module inter_control_module
 7 (
 8     clk, rst_n, trig, sos_en
 9 );
10 
11     input clk;
12     input rst_n;
13     input trig;
14     output sos_en;
15     
16     reg i;
17     reg isen;
18     
19     always @(posedge clk or negedge rst_n)
20         if (!rst_n)
21             begin
22                 i <= 1d0;
23                 isen <= 1b0;
24             end
25         else
26             case (i)
27                 
28                 2d0:
29                 if (trig)
30                     begin
31                         isen <= 1b1;
32                         i <= 1d1;
33                     end
34                 
35                 2d1:
36                 begin
37                     isen <= 1b0;
38                     i <= 1d0;
39                 end
40 
41             endcase
42 
43         assign sos_en = isen;
44 
45 endmodule
46

sos_module.v

1 /**
  2  * File name: sos_module.v
  3  *
  4  */
  5  
  6 module sos_module
  7 (
  8     clk, rst_n, pin_out, sos_en
  9 );
 10 
 11     input clk;
 12     input rst_n;
 13     input sos_en;
 14     output pin_out;
 15     
 16     parameter T1MS = 16d50000 - 1;
 17     
 18     reg [15:0] count;
 19     
 20     always @(posedge clk or negedge rst_n)
 21         if (!rst_n)
 22             count <= 16d0;
 23         else if (iscount && count == T1MS)
 24             count <= 16d0;
 25         else if (iscount)
 26             count <= count + 1b1;
 27         else if (!iscount)
 28             count <= 16d0;
 29             
 30     reg [9:0] count_ms;
 31 
 32     always @(posedge clk or negedge rst_n)
 33         if (!rst_n)
 34             count_ms <= 10d0;
 35         else if (iscount && count == T1MS)
 36             count_ms <= count_ms + 1b1;
 37         else if (!iscount)
 38             count_ms <= 10d0;
 39             
 40     reg iscount;
 41     reg rpin_out;
 42     reg [4:0] i;
 43 
 44     always @(posedge clk or negedge rst_n)
 45         if (!rst_n)
 46             begin
 47                 iscount <= 1b0;
 48                 rpin_out <= 1b0;
 49                 i <= 5d0;
 50             end
 51         else
 52             case(i)
 53                 5d0:
 54                 if (sos_en)
 55                     i <= 5d1;
 56                     
 57                 5d1, 5d3, 5d5,        //short
 58                 5d13, 5d15, 5d17:
 59                 if (count_ms == 10d100)
 60                     begin
 61                         iscount <= 1b0;
 62                         rpin_out <= 1b0;
 63                         i <= i + 1b1;
 64                     end
 65                 else
 66                     begin
 67                         iscount <= 1b1;
 68                         rpin_out <= 1b1;
 69                     end
 70 
 71                 5d7, 5d9, 5d11:    //long
 72                 if (count_ms == 10d300)
 73                     begin
 74                         iscount <= 1b0;
 75                         rpin_out <= 1b0;
 76                         i <= i + 1b1;
 77                     end
 78                 else
 79                     begin
 80                         iscount <= 1b1;
 81                         rpin_out <= 1b1;
 82                     end
 83 
 84                 5d2, 5d4, 5d6,        //interval
 85                 5d8, 5d10, 5d12,
 86                 5d14, 5d16, 5d18:
 87                     if (count_ms == 10d50) 
 88                         begin
 89                             iscount <= 1b0;
 90                             i <= i + 1b1;
 91                         end
 92                     else
 93                         iscount <= 1b1;
 94                         
 95                 5d19:        //end
 96                     begin
 97                         rpin_out <= 1b0;
 98                         i <= 5d0;
 99                     end
100             endcase
101 
102         assign pin_out = rpin_out;
103 
104 endmodule
105         
106                 
107

exp06_top.v

1 /**
 2  * File name : exp06_top.v
 3  * -----------------------
 4  * pins:
 5  * KEY0-rst_n, KEY1-pin_in, LEDG8-pin_out.
 6  * -----------------------
 7  * yf.x
 8  * 7-16-2011
 9  */
10  
11 module exp06_top
12 (
13     CLOCK_50, KEY, LEDG
14 );
15 
16     input CLOCK_50;
17     input [1:0] KEY;
18     output [8:8] LEDG;
19     
20     wire trig;
21     
22     debounce_module2 U1
23     (
24         .clk (CLOCK_50),
25         .rst_n (KEY[0]),
26         .pin_in (KEY[1]),    // input - from top
27         .pin_out ( trig)        // output - to U2
28     );
29 
30     wire sos_en;
31     
32     inter_control_module U2
33     (
34         .clk (CLOCK_50),
35         .rst_n (KEY[0]),
36         .trig (trig),        // input - from U1
37         .sos_en (sos_en)     // output - to U2
38     );
39 
40     sos_module U3
41     (
42         .clk (CLOCK_50),
43         .rst_n (KEY[0]),
44         .sos_en (sos_en),         // input - from U2
45         .pin_out (LEDG)
46     );
47 
48 endmodule
49

RTL图

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小结

由RTL图可以看出，设计上本实验完全可以去掉中间的控制模块，这里，控制模块主要为了说明协调的作用，如果，功能扩展，代码也便于修改。至此，低级建模的基础已描述完毕。